参数资料
型号: MAX8550AETI+T
厂商: Maxim Integrated Products
文件页数: 5/29页
文件大小: 0K
描述: IC PWR SUP DDR INTEG 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 控制器,DDR
输入电压: 2 V ~ 28 V
输出数: 2
输出电压: 1.8V,2.5V,0.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
ELECTRICAL CHARACTERISTICS (continued)
(V IN = +15V, V DD = AV DD = V SHDN = STBY = V BST = V ILIM = 5V, V OUT = V REFIN = V VTTI = 2.5V, UVP/OVP = TP0 = FB = SKIP
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, V VTTS = V VTT , T A = -40°C to +85°C, unless otherwise noted. Typical values
are at T A = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LINEAR REGULATORS (VTTR AND VTT)
VTTI Input Voltage Range
V VTTI
1
2.8
V
VTTI Supply Current
VTTI Shutdown Current
I VTTI
I VTT = I VTTR = 0
SHDN = GND
<0.1
1
10
mA
μA
REFIN Input Impedance
REFIN Range
VTT, VTTR UVLO Threshold
(Measured at OUT)
Soft-Start Charge Current
VTT Internal MOSFET High-Side
On-Resistance
VTT Internal MOSFET Low-Side
On-Resistance
VTT Output Accuracy
(Referred to V REFIN / 2)
VTT Load Regulation
VTT Current Limit
V REFIN
I SS
V REFIN = 2.5V
V SS = 0
I VTT = -100mA, V VTTI = 1.5V,
AV DD = 4.5V
I VTT = 100mA, AV DD = 4.5V
V REFIN = 1.5V or 2.5V, I VTT = 1mA
V REFIN = 2.5V, I VTT = 0 to ± 1.5A
V REFIN = 1.5V, I VTT = 0 to ± 1A
VTT = 0 or VTTI
12
1
0.01
-1
±3
20
0.1
4
1
1
±5
30
2.8
0.20
0.3
0.3
+1
±6.5
k Ω
V
V
μA
Ω
Ω
%
%
A
VTTS Input Current
VTTR Output Error
(Referred to V REFIN / 2)
I VTTS
V VTTS = 1.5V, VTT open
V REFIN = 1.5V or 2.5V, I VTTR = 0
-1
0.1
1
+1
μA
%
VTTR Current Limit
V VTTR = 0 or V VTTI
±18
±32
±50
mA
Note 1: Specifications to -40°C are guaranteed by design, not production tested.
Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level higher than the error-compara-
tor threshold by 50% of the ripple. In discontinuous conduction, the output voltage has a DC regulation level higher than the
trip level by approximately 1.5% due to slope compensation.
Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, V BST = 5V,
and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching speeds.
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