参数资料
型号: MAX8621YETG+T
厂商: Maxim Integrated Products
文件页数: 9/18页
文件大小: 0K
描述: IC PMIC W/DC-DC SUP 24-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 手持/移动设备
电源电压: 2.6 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
供应商设备封装: 24-TQFN-EP(4x4)
包装: 带卷 (TR)
Dual Step-Down DC-DC Power-Management ICs
for Portable Devices
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
NAME
FB1
FB2
GND
REFBP
EN4
OUT4
EN3
EN2
OUT2
IN2
RESET
OUT1
OUT3
PWRON
ENDR
IN3
SEL2
SEL1
DR
FUNCTION
Voltage Feedback for Step-Down Converter 1. FB1 regulates to 0.6V nominal.
Voltage Feedback for Step-Down Converter 2. FB2 regulates to 0.6V nominal.
Ground. Ground for all LDOs and the control section.
Reference Noise Bypass. Connect a 0.01μF ceramic capacitor from REFBP to GND. Not intended to drive resistive
load. REFBP is high impedance in shutdown.
Enable Input for OUT4. Drive EN4 high to turn on OUT4.
150mA LDO4 output. Bypass OUT4 to GND with a 2.2μF ceramic capacitor. OUT4 is high impedance when
disabled. OUT4 can only be activated if OUT1 is within 87% of regulation.
Enable Input for OUT3. Drive EN3 high to turn on OUT3.
Enable Input for OUT2. Drive EN2 high to disable OUT2. Drive EN2 low or leave open to enable OUT2. EN2 is
internally pulled to GND by an 800k Ω (typ) pulldown resistor. If the MAX8621Y/MAX8621Z are placed into shutdown
using PWRON (PWRON = low), OUT2 does not power regardless of the status of EN2 .
300mA LDO2 Output. Bypass with a 4.7μF ceramic capacitor to GND. OUT2 is high impedance when disabled.
OUT2 can only be activated if OUT1 is within 87% of regulation.
Supply Voltage to the Output MOSFET of All 4 LDOs. IN2 must be shorted to IN1 and IN3. Connect a 4.7μF ceramic
capacitor from IN2 to GND.
Open-Drain, Active-Low Reset Output. RESET asserts low when V OUT1 drops below 87% (typ) of regulation. RESET
deasserts 60ms after V OUT1 rises above 87% (typ) of regulation (Figure 2).
300mA LDO1 Output. Bypass with a 4.7μF ceramic capacitor to GND. OUT1 is high impedance when disabled.
150mA LDO3 Output. Bypass OUT3 to GND with a 2.2μF ceramic capacitor. OUT3 is high impedance when
disabled. OUT3 can only be activated if OUT1 is within 87% of regulation.
Power Enable Input. Drive PWRON high to enable the MAX8621Y/MAX8621Z. Drive PWRON low to enter shutdown
mode. PWRON has an internal 800k Ω (typ) pulldown resistor.
Enable Input for DR. Drive ENDR low for DR to go into high impedance. Drive ENDR high to activate DR, pulling
DR low.
Supply Voltage to the Control Section. IN3 must be shorted to IN1 and IN2. Connect a 4.7μF ceramic capacitor from
IN3 to GND.
LDO Output-Voltage Select Input 2. SEL1 and SEL2 set the OUT1, OUT2, OUT3, and OUT4 voltages to one of nine
combinations (Table 1).
LDO Output-Voltage Select Input 1. SEL1 and SEL2 set the OUT1, OUT2, OUT3, and OUT4 voltages to one of nine
combinations (Table 1).
200mA Driver Output. Connects to the open drain of an internal n-channel MOSFET whose gate is controlled by
ENDR.
20
PGND2 Power Ground for BUCK2 and DR Switch
21
22
23
LX2
IN1
LX1
Inductor Connection for BUCK2. LX2 is internally connected to the drain of the internal p-channel MOSFET and the
drain of the internal n-channel synchronous rectifier for BUCK2. LX2 is high impedance when BUCK2 is disabled.
Supply Voltage to the Output Stage of BUCK1 and BUCK2. IN1 must be shorted to IN2 and IN3. Connect a 10μF
ceramic capacitor from IN1 to GND.
Inductor Connection for BUCK1. LX1 is internally connected to the drain of the internal p-channel MOSFET and the
drain of the internal n-channel synchronous rectifier for BUCK1. LX1 is high impedance when BUCK1 is disabled.
24
PGND1 Power Ground for BUCK1
EP
Exposed Paddle. Connect the exposed paddle to GND, PGND1, and PGND2.
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