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参数资料
| 型号： | MAX864EEE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 6/12页 |
| 文件大小： | 0K |
| 描述： | IC REG SWTCHD CAP DBL INV 16QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 切换式电容器（充电泵），倍增器，反相 |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | ±3.5 V ~ ±12 V |
| 输入电压： | 1.75 V ~ 6 V |
| 频率 - 开关： | 185kHz |
| 电流 - 输出： | 35mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-QSOP |
Dual-Output Charge Pump with Shutdown
_______________Detailed Description
The MAX864 requires only four external capacitors to
implement a voltage doubler/inverter. These may be
ceramic or polarized capacitors (electrolytic or tanta-
lum) with values ranging from 0.47μF to 100μF.
Figure 2a illustrates the ideal operation of the positive
voltage doubler. The on-chip oscillator generates a
50% duty-cycle clock signal. During the first half cycle,
switches S2 and S4 open, switches S1 and S3 close,
and capacitor C1 charges to the input voltage (V IN ).
During the second half cycle, switches S1 and S3
open, switches S2 and S4 close, and capacitor C1 is
level shifted upward by V IN volts. Assuming ideal
switches and no load on C3, charge transfers into C3
from C1 such that the voltage on C3 will be 2V IN , gen-
erating the positive supply output (V+).
Figure 2b illustrates the ideal operation of the negative
converter. The switches of the negative converter are
out of phase from the positive converter. During the
second half cycle, switches S6 and S8 open, and
switches S5 and S7 close, charging C2 from V+
(pumped up to 2V IN by the positive charge pump) to
Charge-Pump Frequency
and Capacitor Selection
The MAX864 offers four different charge-pump frequen-
cies. To select a desired frequency, define pins FC0 and
FC1 as shown in Table 1. Lower charge-pump frequen-
cies produce lower average supply currents, while high-
er charge-pump frequencies require smaller capacitors.
Table 1 also lists the recommended charge-pump
capacitor values for each pump frequency. Using val-
ues larger than those recommended will have little
effect on the output current. Using values smaller than
those recommended will reduce the available output
current and increase the output ripple. To cut the out-
put ripple in half, double the values of C3 and C4.
To maintain the lowest output resistance, use capacitors
with low effective series resistance (ESR). At each switch-
ing frequency, the charge-pump output resistance is a
function of C1, C2, C3, and C4’s ESR. Minimizing the
charge-pump capacitors’ ESR minimizes output resis-
tance. Use ceramic capacitors for best results.
Table 1. Frequency Selection
GND. In the first half of the clock cycle, switches S5
and S7 open, switches S6 and S8 close, and the
charge on capacitor C2 transfers to C4, generating the
negative supply. The eight switches are CMOS power
MOSFETs. Switches S1, S2, S4, and S5 are P-channel
devices, while switches S3, S6, S7, and S8 are N-chan-
nel devices.
FC1
0
0
1
1
FC0
0
1
0
1
FREQUENCY
(kHz)
7
33
100
185
CAPACITORS
C1–C4
(μF)
33
6.8
2.2
1
a)
V+
b)
V+
S1
C1+
S2
S5
C2+
S6
IN
GND
C1
C3
I L +
R L +
C2
I L -
R L -
C4
GND
S3
C1-
S4
IN
GND
S7
C2-
S8
V-
Figure 2. Idealized Voltage Quadrupler: a) Positive Charge Pump; b) Negative Charge Pump
6
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