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参数资料
| 型号： | MAX8660ETL+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 35/44页 |
| 文件大小： | 0K |
| 描述： | IC POWER MANAGE XSCALE 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 应用： | 处理器 |
| 电源电压： | 2.6 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 管件 |
| 产品目录页面： | 1411 (CN2011-ZH PDF) |
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High-Efficiency, Low-I Q , PMICs with Dynamic
Voltage Management for Mobile Applications
SDA
SCL
S
t HD;STA
Sr
t SU;STA
t HD;STA
P
t SU;STO
Acknowledge Bit
Both the master and the MAX8660/MAX8661 (slave)
generate acknowledge bits when receiving data. The
acknowledge bit is the last bit of each 9-bit data packet.
To generate an acknowledge (A), the receiving device
must pull SDA low before the rising edge of the acknowl-
edge-related clock pulse (ninth pulse) and keep it low
during the high period of the clock pulse (Figure 9). To
Figure 8. START and STOP Conditions
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing
a START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is a
low-to-high transition on SDA, while SCL is high (Figure 8).
A START condition from the master signals the begin-
ning of a transmission to the MAX8660/MAX8661. The
master terminates transmission by issuing a not-
acknowledge followed by a STOP condition (see the
Acknowledge Bit section for more information). The
STOP condition frees the bus. To issue a series of com-
mands to the slave, the master may issue repeated
start (Sr) commands instead of a stop command in
order to maintain control of the bus. In general, a
repeated start command is functionally equivalent to a
regular start command.
When a STOP condition or incorrect address is detected,
the MAX8660/MAX8661 internally disconnect SCL from
the serial interface until the next START condition, mini-
mizing digital noise and feedthrough.
generate a not acknowledge ( A ), the receiving device
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse and leaves it high
during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a sys-
tem fault has occurred. In the event of an unsuccessful
data transfer, the bus master should reattempt commu-
nication at a later time.
Slave Address
A bus master initiates communication with a slave
device (MAX8660/MAX8661) by issuing a START condi-
tion followed by the slave address. As shown in Figure
10, the slave address byte consists of 7 address bits
and a read/write bit (R/ W ). After receiving the proper
address, the MAX8660/MAX8661 issue an acknowledge
by pulling SDA low during the ninth clock cycle. Note
that the R/ W bit is always zero since the MAX8660/
MAX8661 are write only.
The Marvell PXA3xx processor supports 0x68 (SRAD =
GND) as the I 2 C slave address.
SDA
S
NOT ACKNOWLEDGE
t SU;DAT
ACKNOWLEDGE
t HD;DAT
SCL
1
2
8
9
Figure 9. Acknowledge Bits
SRAD
0 (GND)
SLAVE ADDRESS (WRITE)
BINARY HEXADECIMAL
0b 0110 1000 0x68
R/W = 0
ACKNOWLEDGE
S
1 (IN)
0b 0110 1010
0x6A
(WRITE ONLY)
SDA
SCL
0
1
1
2
1
3
0
4
1
5
0
6
SRAD
7
0
8
A
9
Figure 10. Slave Address Byte
35
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX8660ETL/V+ | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660ETL/V+T | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660ETL+ | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660ETL+T | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660EVKIT+ | 制造商:Maxim Integrated Products 功能描述:MAX8660 EVAL KIT/EVAL SYS - Rail/Tube |
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