- 您现在的位置：买卖IC网 > PDF目录16750 > MAX8661ETL+ (Maxim Integrated Products)IC POWER MANAGE XSCALE 40-TQFN PDF资料下载
参数资料
| 型号： | MAX8661ETL+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 29/44页 |
| 文件大小： | 0K |
| 描述： | IC POWER MANAGE XSCALE 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 应用： | 处理器 |
| 电源电压： | 2.6 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
High-Efficiency, Low-I Q , PMICs with Dynamic
Voltage Management for Mobile Applications
between R RAMP and the output-voltage ramp rates. A
56k ? R RAMP satisfies the typical requirements of
Marvell PXA3xx processors; 200μs after being enabled,
REG3 and REG4 linearly ramp from 0V to the set output
voltage at the rate set by R RAMP . When REG3 and
REG4 are disabled, the output voltage decays at a rate
determined by the output capacitance, internal 550 ?
discharge resistance, and the external load.
Active ramp-down functionality is inherent in forced-
PWM operation. In normal-mode operation, active ramp
down is enabled by setting ARD3 and ARD4 (Table 9).
With “active ramp-down” enabled, the regulator output
voltage ramps down at the rate set by R RAMP . With small
loads, the regulator must sink current from the output
capacitor to actively ramp down the output voltage. In
normal mode, with “active ramp-down” disabled, the
regulator output voltage ramps down at the rate deter-
mined by the output capacitance and the external load;
small loads result in an output-voltage decay that is slow-
er than that specified by R RAMP , large loads (> C OUT x
RAMPRATE) result in an output-voltage decay that is no
faster than that specified by R RAMP .
80μs after being enabled, REG5 linearly ramps from 0V
to the set output voltage in 225μs. The ramp rate during
a positive voltage change (i.e., 1.8V to 1.9V) is set with
R RAMP . During a negative voltage change (i.e., 1.9V to
1.8V), the REG5 output voltage decays at a rate deter-
mined by the output capacitance and the external load;
however, ramp-down is no faster than the rate specified
by R RAMP . When REG5 is disabled, the output voltage
decays at a rate determined by the output capacitance,
internal 2k ? discharge resistance, and the external load.
60μs after being enabled by I 2 C, REG6 and REG7 lin-
early ramp from 0V to the set output voltage in 450μs.
REG6 and REG7 do not have positive voltage-change
Table 5. Enable Signals
(i.e., 1.8V to 2.5V) ramp-rate control. During a positive
voltage change, the output-voltage dV/dt is as fast as
possible. To avoid this fast output dV/dt, disable REG6
or REG7 before changing the output. With this method,
the soft-start ramp rate limits the output dV/dt, and
therefore, the input current is controlled. During a nega-
tive voltage change (i.e., 2.5V to 1.8V), the REG6 or
REG7 output voltage decays at a rate determined by
the output capacitance and the external load. When
REG6 or REG7 is disabled, the output voltage decays
at a rate determined by the output capacitance, internal
350 ? discharge resistance, and the external load.
Power Sequencing
Enable Signals (EN_, PWR_EN, SYS_EN, I 2 C)
As shown in Table 5, the MAX8660/MAX8661 feature
numerous enable signals for flexibility in many applica-
tions. In a typical application with the Marvell PXA3xx
processor, many of these enable signals are connected
together. EN1, EN2, and EN5 typically connect to the
SYS_EN output. With this connection, REG5 is the first
supply to rise (if IN5 is connected to IN). EN34 typically
connects to Marvell’s PWR_EN output. Alternatively,
REG3 and REG4 can be activated by the I 2 C interface
(see the REG3/REG4 Enable (EN34, EN3, EN4) section
for more information). REG6 and REG7 are activated by
the serial interface. REG8 has no enable input and
always remains on as long the MAX8660/MAX8661 are
powered between the UVLO and OVLO range. All regu-
lators are forced off during UVLO and OVLO. See the
Undervoltage and Overvoltage Lockout section for
more information.
Note: The logic that controls the Marvell PXA3xx
processor SYS_EN and PWR_EN signals is powered
from the VCC_BBATT power domain.
POWER DOMAIN
MAXIM ENABLE SIGNAL
HARDWARE SOFTWARE
APPLICATIONS PROCESSOR
ENABLE SIGNAL
V1 ( VCC_IO ) (MAX8660/MAX8660A only)
EN1
—
V2 ( VCC_MEM )
V5 ( VCC_MVT )
V3 ( VCC_APPS )
V4 ( VCC_SRAM )
V6 ( VCC_CARD1 )
V7 ( VCC_CARD2 ) (MAX8660/MAX8660A only)
V8 ( VCC_BBATT )
EN2
EN5
EN34
—
—
—
—
EN3 (OVER1)
EN4 (OVER1)
EN6 (OVER2)
EN7 (OVER2)
Always on
SYS_EN
PWR_EN &
PWR_I 2 C
Standard I 2 C
—
29
相关PDF资料 |
PDF描述 |
|---|---|
| EBC31DCAD | CONN EDGECARD 62POS R/A .100 SLD |
| GCM24DCSD-S288 | CONN EDGECARD 48POS .156 EXTEND |
| M3CCA-1620K | IDC CABLE - MKC16A/MC16F/MKC16A |
| CRN-3/16-0-STK | HEAT SHRINK TUBING |
| EEV-HA0J331XP | CAP ALUM 330UF 6.3V 20% SMD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX8661ETL+ | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8661ETL+T | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8662ETM+ | 功能描述:电池管理 PMIC for Single-Cell Li+ Bat-Operated Dev RoHS:否 制造商:Texas Instruments 电池类型:Li-Ion 输出电压:5 V 输出电流:4.5 A 工作电源电压:3.9 V to 17 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:VQFN-24 封装:Reel |
| MAX8662ETM+T | 功能描述:电池管理 PMIC for Single-Cell Li+ Bat-Operated Dev RoHS:否 制造商:Texas Instruments 电池类型:Li-Ion 输出电压:5 V 输出电流:4.5 A 工作电源电压:3.9 V to 17 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:VQFN-24 封装:Reel |
| MAX8662ETMT | 制造商:MAXIM 功能描述:Pb Free CAT e3 |
发布紧急采购，3分钟左右您将得到回复。