参数资料
型号: MAX8661ETL+
厂商: Maxim Integrated Products
文件页数: 30/44页
文件大小: 0K
描述: IC POWER MANAGE XSCALE 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
应用: 处理器
电源电压: 2.6 V ~ 6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 管件
High-Efficiency, Low-I Q , PMICs with Dynamic
Voltage Management for Mobile Applications
REG3/REG4 Enable (EN34, EN3, EN4)
REG3 and REG4 have independent I 2 C enable bits
(EN3, EN4) and a shared hardware-enable input
(EN34). As shown in Figure 5, the EN34 hardware-
enable input is logically ORed with the I 2 C enable bits.
Table 6 is the truth table for the V3/V4 enable logic.
Note that to achieve a pure I 2 C enable/disable, connect
EN34 to ground. Similarly, to achieve a pure hardware
enable/disable, leave the I 2 C enable bits at their default
value (EN3 = EN4 = 0 = off); V3 and V4 cannot be inde-
pendently enabled/disabled using only hardware.
Note: A low MR drives RSO low and returns the I 2 C
registers to their default values: EN3 = 0 and EN4 = 0.
Power Modes
The MAX8660/MAX8661 provide numerous enable sig-
nals (Table 5) and support any combination for enabling
and disabling their supplies with these signals. Table 7
shows several power modes defined for PXA3xx
processors along with their corresponding MAX8660/
MAX8661 quiescent operating currents.
Power-Up and Power-Down Timing
Figure 6 shows the power-up sequence for the Marvell
PXA3xx family of processors. In general, the supplies
should power up in the following order:
1) POWER-UP: V8 ? V5 ? V1 and V2 ? V3 and V4
2) REG6 and REG7 typically power external card slots
and can be powered up and down based on appli-
cation requirements.
Note that the Marvell PXA3xx processor controls
PV3
BATT
EN1/EN2/EN5 with the same SYS_EN signal, yet Marvell’s
timing diagrams show that V5 is supposed to power up
before V1 and V2. Because of the PXA3xx family’s timing
parameters, most systems connect EN1/EN2/EN5
EN34
REG3
LX3
V3
(VCC_APPS)
together and drive them with SYS_EN. When powering
up, this connection ensures that V5 powers up before
V1 and V2 (only when V5 is powered from IN).
PG3
Marvell PXA3xx Power
ON
Configuration Register (PCFR)
SDA
SCL
EN3
I 2 C
EN4
ON
REG4
PV4
LX4
BATT
V4
(VCC_SRAM)
The MAX8660/MAX8661 comply with the Marvell
PXA3xx power I 2 C register specifications. This allows
the PMIC to be used along with the processor with little-
to-no software development. As shown in Table 9, there
are many I 2 C registers, but since the processor auto-
matically updates the PMIC through its power I 2 C inter-
face, only the REG6 and REG7 enable bits need be
PG4
Figure 5. V3/V4 Enable Logic
Table 6. Truth Table for V3/V4 Enable Logic
HARDWARE INPUT I 2 C BITS
V3 V4
EN34 EN3 EN4
programmed to fully utilize the PMIC.
The Marvell PXA3xx processor contains a power man-
agement unit general configuration register (PCFR).
The default values of this register are compliant with the
MAX8660/MAX8661. However, wake-up performance
can be optimized using this register:
? The PCFR register contains timers for the SYS_DEL
and PWR_DEL timing parameters as shown in Figure
6. Each timer defaults to 125ms. When using the
MAX8660/MAX8661, these timers may be shortened to
2ms to speed up the overall system wake-up delay.
0
0
0
X
1
0 (default)
0
1
1
X
0 (default)
1
0
1
X
OFF
OFF
ON
ON
ON
OFF
ON
OFF
ON
ON
? Enabling the “shorten wake-up delay ” function
(SWDD bit) bypasses the SYS_DEL and PWR_DEL
timers and uses voltage detectors on the Marvell
PXA3xx processor to optimize the overall system
wake-up delay.
X = Don’t care.
30
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MAX8661ETL+ 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel
MAX8661ETL+T 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel
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MAX8662ETM+T 功能描述:电池管理 PMIC for Single-Cell Li+ Bat-Operated Dev RoHS:否 制造商:Texas Instruments 电池类型:Li-Ion 输出电压:5 V 输出电流:4.5 A 工作电源电压:3.9 V to 17 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:VQFN-24 封装:Reel
MAX8662ETMT 制造商:MAXIM 功能描述:Pb Free CAT e3