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参数资料
| 型号： | MAX8664AEEP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 22/26页 |
| 文件大小： | 0K |
| 描述： | IC CNTRLR DUAL OUT 20-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 电源 |
| 电流 - 电源： | 1.4mA |
| 电源电压： | 4.5 V ~ 28 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 20-QSOP |
| 包装： | 带卷 (TR) |
Low-Cost, Dual-Output, Step-Down
Controller with Fast Transient Response
To set the no-load output voltage (V OUT ), calculate the
Finally, calculate the value of Cr as follows:
R 3 = ?
? V OUT FB ? ? R 1 + R 2 ?
? ? ?
( V IN OUT )
? V
value of R3 as follows:
? V FB ? ? R 1 × R 2 ?
? V
Cr =
V OUT
V IN
R 1 × f S × | ( V FB _ RIPPLE ? V OUT _ RIPPLE ) |
where V FB is the feedback regulation voltage (0.6V
when using the internal reference or V REFIN2 for exter-
nal reference). If the desired output voltage is equal to
the reference voltage (typical for tracking applications),
R3 is not installed.
MOSFET Selection
Each output of the MAX8664 is capable of driving two to
four external, logic-level, n-channel MOSFETs as the cir-
cuit switch elements. The key selection parameters are:
? On-resistance (R DS(ON) )—the lower, the better.
To achieve the lowest possible load regulation in appli-
cations where voltage positioning is not desired, R1 is
not installed and R3 is calculated as follows:
?
Maximum Drain-to-Source Voltage (V DSS )—should
be at least 20% higher than the input supply rail at
the high-side MOSFET’s drain.
? × R 2
R 3 = ?
? V FB ?
? V OUT ? V FB ?
Compensation
To ensure stable operation, connect a compensation
capacitor (Cr) across the upper feedback resistor as
shown in Figure 7. To find the value of this capacitor,
follow the compensation design procedure below.
Choose a closed-loop bandwidth (f C ) that is less than
1/3 the switching frequency (f S ). Calculate the output
double pole (f O ) as follows:
? Gate charges (Q g , Q gd , Q gs )— the lower, the better.
For a 5V input application, choose MOSFETs with rated
R DS(ON) at V GS ≤ 4.5V. With higher input voltages, the
internal VL regulator provides 6.5V for gate drive in
order to minimize the on-resistance for a wide range of
MOSFETs.
For a good compromise between efficiency and cost,
choose the high-side MOSFETs that have conduction
losses equal to switching losses at nominal input voltage
and output current. Low R DS(ON) is preferred for low-
side MOSFETs. Make sure that the low-side MOSFET(s)
does not spuriously turn on due to dV/dt caused by the
2 π L × C OUT × LOAD
f O =
1
R + ESR
R LOAD + DCR
high-side MOSFET(s) turning on, as this would result in
shoot-through current and degrade the efficiency.
MOSFETs with a lower Q gd / Q gs ratio have higher
immunity to dV/dt. For high-current applications, it is
The FB peak-to-peak voltage ripple is:
often preferable to parallel two MOSFETs rather than to
use a single large MOSFET.
? R 2 ? ?
? ?
?
× ?
V FB _ RIPPLE = ?
R 2 ? ? ?
? 1 + +
?
R 1 ? ? ? ? ?
?×
?
? R 3
1 +
R 2
R 1
1 +
V OUT
DCR ?
R LOAD ?
f C
f O
?
?
?
?
?
For proper thermal management, the power dissipation
must be calculated at the desired maximum operating
junction temperature, maximum output current, and
worst-case input voltage. For the-low side MOSFET(s),
the worst-case power dissipation occurs at the highest
The output ripple voltage due to the ESR of the output
capacitor, C OUT, is:
duty cycle (V IN(MAX) ). The low-side MOSFET(s) operate
as zero voltage switches; therefore, major losses are
the channel conduction loss (P LSCC ) and the body
× I 2 LOAD ( MAX ) × R DS ( ON )
V IN ( MAX ) ? ?
P LSCC ( MAX ) = ? 1 ?
V OUT _ RIPPLE =
V OUT
V IN
( V IN ? V OUT )
L × f S
×
diode conduction loss (P LSDC ):
? V OUT ?
?
? ESR +
8 × C O S ?
× f
?
?
1 ?
?
Use R DS(ON) at T J(MAX) :
Target the feedback ripple in the 25mV to 60mV range.
For high duty-cycle applications (> 70%), a feedback
ripple of 25mV is recommended.
P LSDC(MAX) = 2 x I LOAD(MAX) V F x t DT x f S
where V F is the body diode forward-voltage drop, t DT is the
dead time between high-side and low-side switching tran-
sitions (25ns typical), and f S is the switching frequency.
22
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