参数资料
型号: MAX8664AEEP+T
厂商: Maxim Integrated Products
文件页数: 24/26页
文件大小: 0K
描述: IC CNTRLR DUAL OUT 20-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 电源
电流 - 电源: 1.4mA
电源电压: 4.5 V ~ 28 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SSOP(0.154",3.90mm 宽)
供应商设备封装: 20-QSOP
包装: 带卷 (TR)
Low-Cost, Dual-Output, Step-Down
Controller with Fast Transient Response
Input Capacitor
The input filter capacitors reduce peak currents drawn
from the power source and reduce noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitors must meet the ripple current
requirement (I RMS ) imposed by the switching currents.
The ripple current requirement can be estimated by the
following equation:
way that the high-side MOSFET’s drain is close and
near the low-side MOSFET’s source. This allows the
input ceramic decoupling capacitor to be placed
directly across and as close as possible to the
high-MOSFET’s drain and the low-side MOSFET’s
source. This helps contain the high switching cur-
rent within this small loop.
3) Pour an analog ground plane in the second layer
I RMS =
1
V IN
( I OUT 1 ) 2 × V OUT 1 × ( V IN ? V OUT 1 ) + ( I OUT 2 ) 2 × V OUT 2 × ( V IN ? V OUT 2 )
underneath the IC to minimize noise coupling.
4) Connect input, output, and VL capacitors to the
Choose a capacitor that exhibits less than 10°C tem-
perature rise at the maximum operating RMS current for
optimum long-term reliability.
Applications Information
PCB Layout Guidelines
Careful PCB layout is an important factor in achieving
low switching losses and clean, stable operation. The
switching power stage requires particular attention.
Follow these guidelines for good PCB layout:
1) A multilayer PCB is recommended.
2) Place IC decoupling capacitors as close as possi-
ble to the IC pins. Keep separate power ground
and signal ground planes. Place the low-side
MOSFETs near the PGND pin. Arrange the high-
side MOSFETs and low-side MOSFETs in such a
power ground plane; connect all other capacitors to
the signal ground plane.
5) Place the MOSFETs as close as possible to the IC
to minimize trace inductance of the gate drive loop.
If parallel MOSFETs are used, keep the trace
lengths to both gates equal and short.
6) Connect the drain leads of the power MOSFET to a
large copper area to help cool the device. Refer to
the power MOSFET data sheet for recommended
copper area.
7) Place the feedback network components as close
as possible to the IC pins.
8) The current-limit setting RC should be Kelvin con-
nected to the high-side MOSFETs’ drain.
Refer to the MAX8664 evaluation kit for an example layout.
24
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