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参数资料
| 型号： | MAX8677CETG+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/21页 |
| 文件大小： | 0K |
| 描述： | IC USB/AC ADP CHARGER 24-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 充电管理 |
| 电池化学： | 锂离子（Li-Ion）、锂聚合物（Li-Pol） |
| 电源电压： | 4.1 V ~ 6.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
1.5A Dual-Input USB/AC Adapter Charger
and Smart Power Selector
ELECTRICAL CHARACTERISTICS (continued)
(V DC = 5V, THM = CEN = USUS = GND, V BAT = 4V, V PEN1 = V PEN2 = 5V, USB, TSET, PREQ , CHG , DOK , UOK , FLT are unconnected,
T A = -40°C to +85°C, unless otherwise noted. Typical values are at T A = +25°C.) (Note 1)
PARAMETER
ISET Voltage
Charger Soft-Start Time
BAT Prequal Threshold
CONDITIONS
R ISET = 4k Ω , I BAT = 500mA
(V ISET = 1.5V at full charge current)
Charge-current ramp time
V BAT rising, 180mV hysteresis
MIN
0.9
2.9
TYP
1.0
1.5
3
MAX
1.1
3.1
UNITS
V
ms
V
BAT Leakage Current
DONE Threshold as a
Percentage of Fast-Charge
V BAT = 4.2V
I BAT decreasing
No DC or USB power connected
DC or USB connected, V CEN = 5V
V TSET = 0
V TSET = open
3
3
5
10
6
6
μA
%
V TSET = V L
15
Maximum Prequal Time
Maximum Fast-Charge Time
From V CEN falling to end of prequal charge,
V BAT = 2.5V, C T = 0.068μF
From V CEN falling to V FLT falling, C T = 0.068μF
30
300
Min
Min
Timer Accuracy
Timer Extend Threshold
Timer Suspend Threshold
C T = 0.068μF
Percentage of fast-charge current below which timer
clock operates at half speed
Percentage of fast-charge current below which timer
clock pauses
-20
50
20
+20
%
%
%
THM
THM Threshold, Cold
THM Threshold, Hot
THM Threshold, Disabled
THM Input Leakage
When charging is suspended, 2% hysteresis
When charging is suspended, 2% hysteresis
When THM function is disabled
THM = GND or V L ; T A = +25°C
THM = GND or V L ; T A = +85°C
72
26
-0.1
74
28
3
0.001
0.01
76
30
+0.2
% of V L
% of V L
% of V L
μA
LOGIC I/O: CHG , FLT , PREQ , DOK , UOK , PEN1, PEN2, CEN , TSET, USUS
Logic Input Thresholds
High level
Low level
Hysteresis
1.3
50
0.4
V
mV
High level
V L - 0.3
TSET Input Threshold
Midlevel
1.2
V L - 1.2
V
Low level
0.3
TSET Input-Bias Current
Logic Input-Leakage Current
Logic Output Voltage, Low
Logic Output-Leakage Current,
High
TSET = GND
TSET = V L
V INPUT = 0 to 5.5V
Sinking 1mA
V OUT = 5.5V
T A = +25°C
T A = +85°C
T A = +25°C
T A = +85°C
-20
-6
6
0.001
0.01
25
0.001
0.01
20
1
100
1
μA
μA
mV
μA
Note 1: Limits are 100% production tested at T A = +25°C. Limits over the operating temperature range are guaranteed by design.
Note 2: Guaranteed by design.
4
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