参数资料
型号: MAX8688ALETG+T
厂商: Maxim Integrated Products
文件页数: 32/38页
文件大小: 0K
描述: IC PWR SUPPLY CTRLR/MONTR 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 电源控制器/监控器
电源电压: 3 V ~ 3.6 V
电流 - 电源: 6.7mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
供应商设备封装: 24-TQFN-EP(4x4)
包装: 带卷 (TR)
Digital Power-Supply Controller/Monitor
with PMBus Interface
Table 8. MFR_MODE Bit Definition (continued)
BIT
5
4
3
2
1
0
BIT NAME
EEPROM Lock
Enable
Correction Bypass
Enable
Input Range Select
ENOUT Polarity
Select
Feedback Mode
Select
Clock Source
Select
DESCRIPTION
The EEPROM Lock Enable bit is used to protect external EEPROM data from being overwritten. When
this bit is set to 1, the STORE_DEFAULT_ALL command is ignored. The RESTORE_DEFAULT_ALL
command is still valid. When this bit is cleared to 0, the STORE_DEFAULT_ALL command initiates a
store configuration operation to the EEPROM attached to A1/SCLE and A2/SDAE.
Correction Bypass Enable. Setting this bit to 1 disables a correction algorithm made to voltage,
current, and temperature readings. Clearing this bit to 0 applies a correction algorithm to voltage,
current, and temperature measurement, thus resulting in high-accuracy readings. For optimal
operation, this bit should be cleared to 0.
The Input Range Select bit determines the input range of RS+ and RS-. Setting this bit to 1 extends
the input range to 5.5V. Clearing this bit to 0 sets the input range to 2.048V.
Prior to setting any voltage-related values, the user application must first configure the desired input
range. All voltage-related commands use the selected input range to convert the commanded value
into internal register values.
It is not recommended to change the input range selection while the POL is operating, since all
voltage-related commands continue to refer to the input range that was in use when the commanded
voltage was received. This results in unpredictable and catastrophic operation.
The ENOUT Polarity Select bit selects the ENOUT active-on polarity. Setting this bit to 1 configures the
ENOUT asserted on-state the same as the default startup state. Clearing this bit to 0 configures the
ENOUT deasserted off-state the same as the default startup state. In effect, writing a 1 to this bit
means that the asserted state of ENOUT is the default startup state. See the ENOUT Operation
section.
The Feedback Mode Select bit determines the MAX8688 operation mode. When this bit is set to 1, the
MAX8688 operates in the feedback mode while when cleared to 0, the MAX8688 operates in the
REFIN mode.
The Clock Source Select bit determines the MAX8688 reference clock time source. When the Clock
Source Select bit is set to 1, an external clock must be supplied to CLKIO and is used as the
MAX8688 reference clock. When this bit is cleared to 0, an internal clock is used.
MFR_VOUT_CORRECTION_RATE (D2h)
The MFR_VOUT_CORRECTION_RATE command sets
the frequency (Hz) at which the MAX8688 adjusts 1
LSB of DACOUT (0.5mV) after the voltage has entered
the regulation band.
Correction Rate = 10kHz/MFR_VOUT_CORRECTION_RATE
The 2 data bytes are formatted as positive integers. Valid
values are from 1 to 65535. Setting this value to 0 dis-
ables the DACOUT adjustment in the regulation band.
The default MFR_VOUT_CORRECTION_RATE value is
10 which is equivalent to a correction rate of 1kHz.
MFR_SAMPLE_RATE (D3h)
The MFR_SAMPLE_RATE command sets the frequency
(Hz) at which the POL output voltage, output current,
and temperature fault/warning conditions are monitored.
Monitor Sample Rate =10kHz/MFR_SAMPLE_RATE
The 2 data bytes are formatted as positive integers.
Valid values are from 1 to 65535. Setting this value to 0
disables all fault/warning monitoring.
The default MFR_SAMPLE_RATE value is 50 which is
equivalent to a sample rate of 200Hz.
32
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