参数资料
型号: MAX8720EEI+T
厂商: Maxim Integrated Products
文件页数: 20/31页
文件大小: 0K
描述: IC CNTRL VID STP DWN 28-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 控制器,CPU GPU
输入电压: 2 V ~ 28 V
输出数: 1
输出电压: 0.28 V ~ 1.85 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-QSOP
供应商设备封装: 28-QSOP
包装: 带卷 (TR)
Dynamically Adjustable 6-Bit VID
Step-Down Controller
Table 5. Suspend-Mode DAC Codes
tional clock period. The total time for a transition
depends on R TIME , the voltage difference, and the
S1
GND
GND
GND
GND
REF
REF
S0
GND
REF
OPEN
V CC
GND
REF
V OUT
0.650
0.625
0.600
0.575
0.550
0.525
S1
OPEN
OPEN
OPEN
OPEN
V CC
V CC
S0
GND
REF
OPEN
V CC
GND
REF
V OUT
0.450
0.425
0.400
0.375
0.350
0.325
accuracy of the MAX8720’s slew-rate clock, and is not
dependent on the total output capacitance. The greater
the output capacitance, the higher the surge current
required for the transition. The MAX8720 automatically
controls the current to the minimum level required to
complete the transition in the calculated time, as long
as the surge current is less than the current limit set by
ILIM. The transition time is given by:
REF
REF
OPEN
V CC
0.500
0.475
V CC
V CC
OPEN
V CC
0.300
0.275
t TRANS =
| V OLD ? V NEW |
25 mV × f SLEW
+ t DELAY
When the CPU suspends operation (SUS = high), the
controller overrides the 6-bit VID DAC code set by
D0–D5, and slews the output voltage to the target volt-
age set by the S0, S1 inputs. During the transition, the
MAX8720 blanks both PGOOD thresholds (PGOOD
forced high impedance) until the slew-rate controller
reaches the suspend-mode voltage, plus 8 extra R TIME
clocks. After this blanking time expires, the MAX8720
automatically switches to a pulse-skipping control
scheme regardless of SKIP .
Output-Voltage-Transition Timing
The MAX8720 is designed to perform output-voltage
transitions in a controlled manner, automatically mini-
mizing input surge currents. This feature allows the cir-
cuit designer to achieve nearly ideal transitions,
guaranteeing just-in-time arrival at the new output-volt-
age level with the lowest possible peak currents for a
given output capacitance. This makes the IC ideal for
CPUs and GPUs that operate at different voltages.
At the beginning of an output-voltage transition (VID
change or SUS level change), the MAX8720 enters
forced-PWM mode and blanks the PGOOD output
(forced high impedance). PGOOD remains blanked
during the transition and is re-enabled when the slew-
rate controller has set the internal DAC to the final value
and 8 additional slew-rate clock periods have passed.
The slew-rate clock frequency (set by resistor R TIME )
must be set fast enough to ensure that the longest
required transition is completed within the allowed tran-
sition time.
The output-voltage transition is performed in 25mV
steps, preceded by a delay and followed by one addi-
where f SLEW = 150kHz x 120k ? / R TIME , V OLD is the
original DAC setting, V NEW is the new DAC setting, and
t DELAY ranges from zero to a maximum of 2 / f SLEW .
See Time Frequency Accuracy in the Electrical Char-
acteristics table for f SLEW accuracy. The practical
range of R TIME is 22k ? to 470k ? , corresponding to
1.22μs to 26μs per 25mV step. Although the DAC takes
discrete 25mV steps, the output filter makes the transi-
tions relatively smooth. The average inductor current
required to make an output-voltage transition is:
I L ( AVE ) = C OUT × 25 mV × f SLEW
Suspend Transition
(Forced-PWM Operation Selected)
When the MAX8720 enters suspend mode while config-
ured for forced-PWM operation ( SKIP pulled high), the
controller ramps the output voltage down to the S0, S1
programmed voltage at the slew rate determined by
R TIME . The controller blanks PGOOD (forced high
impedance) until the transition is completed plus 8 extra
R TIME clocks—the internal target voltage equals the
selected S0, S1 DAC voltage. After this blanking time
expires, the controller enters pulse-skipping operation.
When exiting suspend mode (SUS pulled low), the
MAX8720 immediately enters forced-PWM mode and
ramps the output up at the slew rate set by R TIME . The
controller blanks PGOOD (forced high impedance) until
the transition is completed plus 8 extra R TIME clocks—
the internal target voltage equals the selected D0–D5
DAC voltage.
20
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