参数资料
型号: MAX8730ETI+T
厂商: Maxim Integrated Products
文件页数: 27/29页
文件大小: 0K
描述: IC CHARGER BATTERY 28-TQFN
标准包装: 2,500
功能: 充电管理
电池化学: 多化学
电源电压: 8 V ~ 28 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
Low-Cost Battery Charger
REF
R7
R14
ICTL
R8
Figure 12. ICTL Foldback Current Adjustment
For typical applications, choose t Delay = 20μs
(depends on the p-MOSFET selected for the PDS
switch).
The following components can be used for a 10A sys-
tem short-current design:
R10 = 8.66k ?
C6 = 0.1μF
R15 = 7.15k ?
C13 = 2.7nF
Foldback Current
At low duty cycles, most of the charge current is con-
ducted through the Schottky diode (D1). To reduce the
requirements of the Schottky diode, the MAX8730 has a
foldback charge current feature. When the battery volt-
age falls below 5 x V RELTH , ICTL sinks 6μA. Add a
series resistor to ICTL to adjust the charge current fold-
back, as shown in Figure 12:
Good PC board layout is required to achieve specified
noise immunity, efficiency, and stable performance.
The PC board layout artist must be given explicit
instructions—preferably, a sketch showing the place-
ment of the power-switching components and high-
current routing. Refer to the PC board layout in the
MAX8730 evaluation kit for examples.
Use the following step-by-step guide:
1) Place the high-power connections first, with their
grounds adjacent:
? Minimize the current-sense resistor trace lengths,
and ensure accurate current sensing with Kelvin
connections.
? Minimize ground trace lengths in the high-current
paths.
? Minimize other trace lengths in the high-current
paths.
? Use > 5mm wide traces in the high-current
paths.
? Connect to the input capacitors directly to the
source of the high-side MOSFET (10mm max
length). Place the input capacitor between the
input current-sense resistor and the source of the
high-side MOSFET.
2) Place the IC and signal components. Quiet connec-
tions to REF, CCV, CCI, CCS, ACIN, SWREF, and
LDO SRC should be returned to a separate ground
(GND) island. There is very little current flowing in
these traces, so the ground island need not be very
large. When placed on an inner layer, a sizable
ground island can help simplify the layout because
the low current connections can be made through
vias. The ground pad on the backside of the pack-
age should be the star connection to this quiet
??
x V REF ? FOLDBACK
?? ?
?
R1 4 =
1 ? R8
6 μ A ? R7 + R8
I          x R S2 x 3.6V ?
1 3 5m V
R8 x R7
R7 + R8
ground island.
3) Keep the gate drive trace (DHI) and SRC path as
short as possible (L < 20mm), and route them away
from the current-sense lines and REF. Bypass DHIV
directly to the source of the high-side MOSFET.
Layout and Bypassing
Bypass SRC, ASNS, LDO, DHIV, and REF as shown in
Figure 1.
These traces should also be relatively wide (W >
1.25mm).
4) Place ceramic bypass capacitors close to the IC.
The bulk capacitors can be placed further away.
______________________________________________________________________________________
27
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