参数资料
型号: MAX8744ETJ+T
厂商: Maxim Integrated Products
文件页数: 14/36页
文件大小: 0K
描述: IC CNTRLR PWR SUP QUAD 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 控制器,笔记本电脑电源系统
输入电压: 6 V ~ 26 V
输出数: 4
输出电压: 3.3V,5V,1 V ~ 26 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Pin Description (continued)
PIN
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NAME
BST5
DH5
LX5
DL5
PGND
LDO5
IN
PGOODA
DL3
LX3
DH3
BST3
PGOOD3
CSL3
CSH3
FB3
FUNCTION
Boost Flying Capacitor Connection for the 5V SMPS. The MAX8744/MAX8745 include an internal
boost switch connected between LDO5 and BST5. Connect to an external capacitor as shown in
Figure 1.
High-Side Gate-Driver Output for the 5V SMPS. DH5 swings from LX5 to BST5.
Inductor Connection for the 5V SMPS. Connect LX5 to the switched side of the inductor. LX5 serves
as the lower supply rail for the DH5 high-side gate driver.
Low-Side Gate-Driver Output for the 5V SMPS. DL5 swings from PGND to LDO5.
Power Ground
5V Internal Linear-Regulator Output. Bypass with 4.7μF minimum (1μF/25mA). Provides at least
100mA for the DL_ low-side gate drivers, the DH_ high-side drivers through the BST switches, the
PWM controller, logic, reference, and external loads. If CSL5 is greater than 4.5V and soft-start is
complete, the linear regulator shuts down, and LDO5 connects to CSL5 through a 1 Ω switch rated for
loads up to 200mA.
Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator. Bypass to PGND with a
0.22μF or greater ceramic capacitor close to the IC.
Open-Drain, Power-Good Output for the Auxiliary LDO. PGOODA is pulled low if FBA drops more
than 10% (typ) below the normal regulation point, and when the auxiliary LDO is shut down. PGOODA
becomes high impedance when FBA is in regulation.
Low-Side Gate-Driver Output for the 3.3V SMPS. DL3 swings from PGND to LDO5.
Inductor Connection for the 3.3V SMPS. Connect LX3 to the switched side of the inductor. LX3 serves
as the lower supply rail for the DH3 high-side gate driver.
High-Side Gate-Driver Output for the 3.3V SMPS. DH3 swings from LX3 to BST3.
Boost Flying Capacitor Connection for the 3.3V SMPS. The MAX8744/MAX8745 include an internal
boost switch connected between LDO5 and BST3. Connect to an external capacitor as shown in
Figure 1.
Open-Drain, Power-Good Output for the 3.3V SMPS. PGOOD3 is pulled low if CSL3 drops more than
10% (typ) below the normal regulation point. PGOOD3 is held low during soft-start and shutdown.
PGOOD3 becomes high impedance when CSL3 is in regulation.
Output Sense and Negative Current Sense for the 3.3V SMPS. When using the internal preset 3.3V
feedback divider (FB3 = LDO5), the controller uses CSL3 to sense the output voltage. Connect to the
negative terminal of the current-sense element.
Positive Current-Sense Input for the 3.3V SMPS. Connect to the positive terminal of the current-sense
element. Figure 7 describes two different current-sensing options—using accurate sense resistors or
lossless inductor DCR sensing.
Feedback Input for the 3.3V SMPS. Connect to LDO5 for fixed 3.3V output. In adjustable mode, FB3
regulates to 2V.
14
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