参数资料
型号: MAX8760ETL+T
厂商: Maxim Integrated Products
文件页数: 24/39页
文件大小: 0K
描述: IC CNTRLR QUICK PWM 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 控制器,6 位 VID AMD 移动式 Turion?
输入电压: 4 V ~ 28 V
输出数: 2
输出电压: 0.38 V ~ 1.55 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 带卷 (TR)
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
Table 5. Suspend Mode DAC Codes
LOWER SUSPEND CODES
UPPER SUSPEND CODES
SUS
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
S1
GND
GND
GND
GND
REF
REF
REF
REF
OPEN
OPEN
OPEN
OPEN
V CC
V CC
V CC
V CC
S0
GND
REF
OPEN
V CC
GND
REF
OPEN
V CC
GND
REF
OPEN
V CC
GND
REF
OPEN
V CC
OUTPUT
VOLTAGE (V)
0.800
0.775
0.750
0.725
0.700
0.675
0.650
0.625
0.600
0.575
0.550
0.525
0.500
0.475
0.450
0.425
SUS
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
S1
GND
GND
GND
GND
REF
REF
REF
REF
OPEN
OPEN
OPEN
OPEN
V CC
V CC
V CC
V CC
S0
GND
REF
OPEN
V CC
GND
REF
OPEN
V CC
GND
REF
OPEN
V CC
GND
REF
OPEN
V CC
OUTPUT
VOLTAGE (V)
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
* Connect the tri-level SUS input to a 2.7V or greater supply (3.3V or V CC ) for an input logic level high.
Multiphase Quick-PWM
5V Bias Supply (V CC and V DD )
The Quick-PWM controller requires an external 5V bias
supply in addition to the battery. Typically, this 5V bias
supply is the notebook’s 95%-efficient 5V system sup-
ply. Keeping the bias supply external to the IC
improves efficiency and eliminates the cost associated
with the 5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the 5V bias supply
can be generated with an external linear regulator.
The 5V bias supply must provide V CC (PWM controller)
and V DD (gate-drive power), so the maximum current
drawn is:
I BIAS = I CC + f SW (Q G(LOW) + Q G(HIGH) )
where I CC is provided in the Electrical Characteristics
table, f SW is the switching frequency, and Q G(LOW) and
Q G(HIGH) are the MOSFET data sheet’s total gate-charge
specification limits at V GS = 5V.
V+ and V DD can be connected together if the input
power source is a fixed 4.5V to 5.5V supply. If the 5V
bias supply is powered up prior to the battery supply,
the enable signal ( SHDN going from low to high) must
be delayed until the battery voltage is present to ensure
startup.
Free-Running, Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudofixed-
frequency, constant-on-time, current-mode regulator with
input voltage feed-forward (Figure 5). This architecture
relies on the output filter capacitor’s ESR to act as the
current-sense resistor, so the output ripple voltage pro-
vides the PWM ramp signal. The control algorithm is sim-
ple: the high-side switch on-time is determined solely by
a one-shot with a period inversely proportional to input
voltage, and directly proportional to output voltage or the
difference between the main and secondary inductor
currents (see the On-Time One-Shot ( TON ) section).
Another one-shot sets a minimum off-time. The on-time
one-shot triggers when the error comparator goes low,
the inductor current of the selected phase is below the
valley current-limit threshold, and the minimum off-time
one-shot times out. The controller maintains 180° out-of-
phase operation by alternately triggering the main and
secondary phases after the error comparator drops
below the output voltage set point.
24
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