参数资料
型号: MAX8760ETL+T
厂商: Maxim Integrated Products
文件页数: 34/39页
文件大小: 0K
描述: IC CNTRLR QUICK PWM 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 控制器,6 位 VID AMD 移动式 Turion?
输入电压: 4 V ~ 28 V
输出数: 2
输出电压: 0.38 V ~ 1.55 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 带卷 (TR)
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
? ? I
? C f
PD ( N H SWITCHING ) = ( V IN ( MAX ) ) 2 ? RSS SW ? ? LOAD ?
I LOAD = η TOTAL ? I VALLEY ( MAX ) + ?
? ? I
? V
PD ( N H RESISTIVE ) = ? OUT ? ? LOAD ? R DS ( ON )
= η TOTAL I VALLEY ( MAX ) + ? LOAD ( MAX )
?
?
?
cuit longevity.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (>20V) AC adapters. Low-cur-
rent applications usually require less attention.
The high-side MOSFET (N H ) must be able to dissipate
the resistive losses plus the switching losses at both
V IN(MIN) and V IN(MAX) . Calculate both of these sums.
Ideally, the losses at V IN(MIN) should be roughly equal to
losses at V IN(MAX) , with lower losses in between. If the
losses at V IN(MIN) are significantly higher than the losses
at V IN(MAX) , consider increasing the size of N H (reducing
R DS(ON) but with higher C GATE ). Conversely, if the losses
at V IN(MAX) are significantly higher than the losses at
V IN(MIN) , consider reducing the size of N H (increasing
R DS(ON) to lower C GATE ). If V IN does not vary over a wide
range, the minimum power dissipation occurs where the
resistive losses equal the switching losses.
Choose a low-side MOSFET that has the lowest possible
on-resistance (R DS(ON) ), comes in a moderate-sized
package (i.e., one or two 8-pin SOs, DPAK, or D 2 PAK),
and is reasonably priced. Ensure that the DL gate driver
can supply sufficient current to support the gate charge
and the current injected into the parasitic gate-to-drain
capacitor caused by the high-side MOSFET turning on;
otherwise, cross-conduction problems can occur (see
the MOSFET Gate Driver section).
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N H ), the worst-
case power dissipation due to resistance occurs at the
minimum input voltage:
? 2
? V IN ? ? η TOTAL ?
where η TOTAL is the total number of phases.
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R DS(ON) required to stay within package
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (R DS(ON) ) losses. High-
side switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation in high-side MOSFET
(N H ) due to switching losses is difficult since it must
allow for difficult quantifying factors that influence the
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold
voltage, source inductance, and PC board layout
characteristics. The following switching-loss calculation
provides only a very rough estimate and is no substi-
tute for breadboard evaluation, preferably including
verification using a thermocouple mounted on N H :
?
? I GATE ? ? η TOTAL ?
where C RSS is the reverse transfer capacitance of N H
and I GATE is the peak gate-drive source/sink current
(1A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied due to the squared term in the C x
V IN 2 x f SW switching-loss equation. If the high-side
MOSFET chosen for adequate R DS(ON) at low battery
voltages becomes extraordinarily hot when biased from
V IN(MAX) , consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (N L ), the worst-case power
dissipation always occurs at maximum input voltage:
? ? V OUT ? ? ? I LOAD ? 2
PD ( N L RESISTIVE ) = ? 1 ? ? ? ? ? ? R DS ( ON )
? ? V IN ( MAX ) ? ? ? η TOTAL ?
The worst-case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I LOAD(MAX) but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “overdesign” the
circuit to tolerate:
? ? I INDUCTOR ?
? 2 ?
? I LIR ?
2
where I VALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-size heatsink to handle the overload
power dissipation.
Choose a Schottky diode (D L ) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. As a gen-
eral rule, select a diode with a DC current rating equal
to 1/3 of the load current-per-phase. This diode is
optional and can be removed if efficiency is not critical.
Boost Capacitors
The boost capacitors (C BST ) must be selected large
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1μF ceramic
34
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