参数资料
型号: MAX8790AETP+T
厂商: Maxim Integrated
文件页数: 15/23页
文件大小: 0K
描述: IC LED DRVR WHITE BCKLGT 20-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
拓扑: PWM,升压(升压)
输出数: 6
内部驱动器:
类型 - 主要: 背光
类型 - 次要: 白色 LED
频率: 1MHz
电源电压: 4.5 V ~ 5.5 V,5.5 V ~ 26 V
输出电压: 5V
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP
包装: 带卷 (TR)
工作温度: -40°C ~ 85°C
Six-String White LED Driver with Active
Current Balancing for LCD Panel Applications
I LED max =
f PLL =
In  digital  dimming  mode,  the  step-up  controller  and
current source are directly turned on and off by the
PWM signal. The current pulse magnitude, or full-scale
current, is set by ISET and is independent of PWM duty
factor. The current-source outputs are PWM signals
synchronized to the BRT input signal (see Figure 5).
The full-scale current in both methods is specified by
resistance from the ISET pin to ground:
20mA × 100k Ω
R ISET
The acceptable resistance range is 74k Ω < R ISET <
133k Ω , which corresponds to full-scale LED current of
27mA > I LEDmax > 15mA. Connect ISET to V CC for a
default full-scale LED current of 20mA. When ENA is
high, the analog dimming is enabled, when ENA is low,
digital dimming is enabled.
When the current-source output is pulse-width modulated,
current-source turn-on is synchronized with the BRT
signal. Synchronization and low jitter in the PWM sig-
nals help reduce flicker noise in the display. The cur-
rent through each FB_ pin is controlled only during the
step-up converter’s on-time. During the converter’s off-
time, the current sources are turned off. The output volt-
age does not discharge and stays high. Each FB_ pin can
withstand 28V, which is the pin’s maximum rated voltage.
Table 2 summarizes the characteristics of both analog
and digital dimming methods.
A PLL translates the duty cycle of the BRT input into a
reference for the MAX8790A’s current sources. A resis-
tor from the FSET pin to ground controls the PLL’s free-
running frequency:
1
10 × R FSET × 800 pF
The PLL’s loop filter bandwidth is set with a capacitor
from the CPLL pin to ground. This filter integrates the
phase difference between the BRT input signal and the
PLL oscillator. The filter bandwidth determines the
PLL’s dynamic response to frequency changes in the
BRT signal. For most applications, a 0.1μF capacitor is
adequate for oscillator frequencies in the 166Hz < f PLL
< 500Hz range. The PLL frequency capture window is
0.6 x f PLL to f PLL .
D=
t ON
t BRT
DPWM DIMMING MODE
BRT
D = 50%
t ON
D = 30%
D = 12.5%
D = 6.25%
t BRT
I LEDMAX
I LED
0A
Figure 5. LED Current Control Using DPWM Dimming Mode
Table 2. Dimming Mode
MODE
ENA
PLL FREQUENCY
CPLL
DESCRIPTION
Analog dimming from 100% to 12.5% brightness. From 12.5% to
Analog + DPWM
> 2.1V
250k Ω < R FSET < 754k Ω
0.1μF
1% brightness, DPWM dimming is employed. BRT frequency
range is 100Hz to 500Hz.
Direct DPWM
< 0.8V
V FSET > V CC - 0.4V,
disables PLL
OPEN
Direct dimming by BRT signal. BRT frequency can be 100Hz to
2kHz; 50μs minimum BRT on-time limits the minimum brightness.
______________________________________________________________________________________
15
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