参数资料
型号: MAX8790AETP+T
厂商: Maxim Integrated
文件页数: 21/23页
文件大小: 0K
描述: IC LED DRVR WHITE BCKLGT 20-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
拓扑: PWM,升压(升压)
输出数: 6
内部驱动器:
类型 - 主要: 背光
类型 - 次要: 白色 LED
频率: 1MHz
电源电压: 4.5 V ~ 5.5 V,5.5 V ~ 26 V
输出电压: 5V
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP
包装: 带卷 (TR)
工作温度: -40°C ~ 85°C
Six-String White LED Driver with Active
Current Balancing for LCD Panel Applications
PCB Layout Guidelines
Careful PCB layout is important for proper operation. Use
the following guidelines for good PCB layout:
1) Minimize the area of the high current-switching loop
of the rectifier diode, external MOSFET, sense resis-
tor, and output capacitor to avoid excessive switching
noise. Use wide and short traces for the gate-drive
loop from the EXT pin, to the MOSFET gate, and
through the current-sense resistor, then returning to
the IC GND pin.
2) Connect high-current input and output components
with short and wide connections. The high-current
input loop goes from the positive terminal of the input
capacitor to the inductor, to the external MOSFET,
then to the current-sense resistor, and to the input
capacitor’s negative terminal. The high-current out-
put loop is from the positive terminal of the input
capacitor to the inductor, to the rectifier diode, to
the positive terminal of the output capacitors,
5) Place the IN pin bypass capacitor as close to the
device as possible. The ground connection of the
IN bypass capacitor should be connected directly
to GND pins with a wide trace.
6) Minimize the size of the LX node while keeping it
wide and short. Keep the LX node away from the
feedback node and ground. If possible, avoid run-
ning the LX node from one side of the PCB to the
other. Use DC traces as shields, if necessary.
7) Refer to the MAX8790A evaluation kit for an exam-
ple of proper board layout.
Pin Configuration
TOP VIEW
reconnecting between the output capacitor and
15
14
13
12
11
input capacitor ground terminals. Avoid using vias
in the high-current paths. If vias are unavoidable,
IN 16
10
FB5
use multiple vias in parallel to reduce resistance
and inductance.
CCV 17
9
FB4
3) Create a ground island (PGND) consisting of the
input and output capacitor ground and negative ter-
minal of the current-sense resistor. Connect all
these together with short, wide traces or a small
ground plane. Maximizing the width of the power
ISET 18
FSET 19
CPLL 20
MAX8790AETP+
8
7
6
GND
FB3
FB2
ground traces improves efficiency and reduces out-
put-voltage ripple and noise spikes. Create an ana-
1
2
3
4
5
log ground island (AGND) consisting of the
overvoltage detection-divider ground connection,
the ISET and FSET resistor connections, CCV and
CPLL capacitor connections, and the device ’s
exposed backside pad. Connect the AGND and
PGND islands by connecting the GND pins directly
to the exposed backside pad. Make no other con-
nections between these separate ground planes.
4) Place the overvoltage detection-divider resistors as
close to the OV pin as possible. The divider’s cen-
ter trace should be kept short. Placing the resistors
far away causes the sensing trace to become
antennas that can pick up switching noise. Avoid
running the sensing traces near LX.
4mm x 4mm THIN QFN
Chip Information
TRANSISTOR COUNT: 12,042
PROCESS: BiCMOS
______________________________________________________________________________________
21
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