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参数资料
| 型号： | MAX8811EEE+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 9/11页 |
| 文件大小： | 0K |
| 描述： | IC DRVR DL PHASE HS 16-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 配置： | 高端和低端，同步 |
| 输入类型： | 差分 |
| 延迟时间： | 20ns |
| 电流 - 峰： | 6A |
| 配置数： | 4 |
| 输出数： | 4 |
| 电源电压： | 4.5 V ~ 7 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
High-Speed, Dual-Phase Driver
with Integrated Boost Diodes
PCB Layout
The MAX8811 sources and sinks large currents to drive
MOSFETs at high switching speeds. The high di/dt can
cause unacceptable ringing if the trace lengths and
impedances are not well controlled. The following PCB
layout guidelines are recommended when designing
with the MAX8811:
1) Place all decoupling capacitors as close to their
respective pins as possible.
2) Minimize the high-current loops from the input capac-
itor, upper switching MOSFET, and low-side MOSFET
back to the input capacitor negative terminal.
4) Connect PGND1 and PGND2 as close as possible
to the source of the low-side MOSFETs.
5) Keep LX1 and LX2 away from sensitive analog com-
ponents and nodes.
6) Gate drive traces should be at least 20 mils wide,
kept as short as possible, and tightly coupled to
reduce EMI and ringing induced by high-frequency
gate noise. Adjacent DH_ and LX_ traces should be
tightly coupled.
A sample evaluation layout is available in the MAX8811
Evaluation Kit.
3) Provide enough copper area at and around the
switching MOSFETs and inductors to aid in thermal
dissipation.
PROCESS: BiCMOS
Chip Information
_______________________________________________________________________________________
9
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