参数资料
型号: MAX8939EWV+T
厂商: Maxim Integrated Products
文件页数: 25/45页
文件大小: 0K
描述: IC PWR MGMT HANDSETS 30WLP
标准包装: 2,500
应用: 充电泵,无线设备
输入电压: 2.9 V ~ 5.5 V
输出数: 7
工作温度: -40°C ~ 85°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
MAX8939/MAX8939A/MAX8939B
System Power Management
for Mobile Handset
V
V BATT
3.0V
2.5V
1.3V
SDA
SCL
PWM
Figure 9. Vibrator Driver PWM Output
DATA LINE STABLE
DATA VALID
Figure 11. I 2 C Bit Transfer
CHANGE OF
DATA ALLOWED
SDA
SDA
SCL
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
START CONDITION
STOP CONDITION
Figure 10. I 2 C Master/Slave Configuration
When the vibrator is disabled, an nFET switch turns
on and shorts the vibrator to ground. At the same time
the nFET switch works as a recovery diode to protect
against reverse voltage from the vibrator.
The ICs include current protection that limits the current
in case the vibrator motor locks up.
Thermal Shutdown
The ICs monitor the die temperature at the charger and
each LDO and DC-DC regulator. When the temperature
exceeds +160 N C, the individual regulator is shutdown
is shutdown. Once the die cools by 20 N C, the regulator
may be reenabled through the I 2 C interface.
The charger has independent thermal control circuitry
that lowers the charge current to regulate the die tem-
perature during the charge. The charger cannot exceed
a temperature higher than the programmed level (default
+100 N C, +115 N C max).
I 2 C Serial Interface
The serial bus consists of a bidirectional serial-data line
(SDA) and a serial-clock input (SCL). See Figure 10.
The ICs are slave-only devices, relying upon a master
to generate the clock signal. The master initiates data
transfer on the bus and generates SCL to permit data
Maxim Integrated
Figure 12. I 2 C START and STOP Conditions
transfer. The I 2 C slave address is 0x62 for write opera-
tions and 0x63 for read operations.
I 2 C is an open-drain bus. SDA and SCL require pullup
resistors (500 I or greater). Optional (24 I ) resistors
in series with SDA and SCL protect the IC inputs from
high-voltage spikes on the bus lines. Series resistors
also minimize crosstalk and undershoot on bus signals.
Data Transfer
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high peri-
od of the SCL clock pulse (see Figure 11). Changes in
SDA while SCL is high are control signals (see the START
and STOP Conditions section for more information).
Each transmit sequence is framed by a START (S) con-
dition and a STOP (P) condition. Each data packet is 9
bits long; 8 bits of data followed by the acknowledge bit.
The ICs support data transfer rates with SCL frequencies
up to 400kHz.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing a
START condition. A START condition is a high-to-low tran-
25
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