参数资料
型号: MAX8939EWV+T
厂商: Maxim Integrated Products
文件页数: 26/45页
文件大小: 0K
描述: IC PWR MGMT HANDSETS 30WLP
标准包装: 2,500
应用: 充电泵,无线设备
输入电压: 2.9 V ~ 5.5 V
输出数: 7
工作温度: -40°C ~ 85°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
MAX8939/MAX8939A/MAX8939B
System Power Management
for Mobile Handset
sition on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA, while SCL is high (Figure 12).
A START condition from the master signals the begin-
ning of a transmission to the ICs. The master terminates
transmission by issuing a not acknowledge followed by a
STOP condition (see the Acknowledge section for more
information). The STOP condition frees the bus. To issue
a series of commands to the slave, the master may issue
REPEATED START (Sr) commands instead of a STOP
command to maintain control of the bus. In general, a
REPEATED START command is functionally equivalent
to a regular start command.
When a STOP condition or incorrect address is detected,
the ICs internally disconnect SCL from the serial inter-
face until the next START condition, minimizing digital
noise and feedthrough.
Acknowledge
Both the master and the ICs (slave) generate acknowl-
edge bits when receiving data. The acknowledge bit is
the last bit of each 9-bit data packet. To generate an
acknowledge (A), the receiving device must pull SDA
low before the rising edge of the acknowledge-related
clock pulse (ninth pulse) and keep it low during the high
period of the clock pulse (Figure 13). To generate a not
acknowledge (NA), the receiving device allows SDA to
be pulled high before the rising edge of the acknowl-
edge-related clock pulse and leaves it high during the
high period of the clock pulse.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
SDA OUTPUT
FROM
TRANSMITTER
SDA OUTPUT
FROM
RECEIVER
D7
D6
D0
NOT ACKNOWLEDGE
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communica-
tion at a later time.
Slave Address
SCL FROM
MASTER
1
2
8
9
ACKNOWLEDGE
A bus master initiates communication with a slave device
(ICs) by issuing a START condition followed by the slave
address. The slave address byte consists of 7 address bits
START CONDITION
CLOCK PULSE FOR
ACKNOWLEDGEMENT
(0110001) and a read/write bit (R/ W ). After receiving the
proper address, the ICs issue an acknowledge by pulling
SDA low during the ninth clock cycle.
Figure 13. I 2 C Acknowledge
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
A. WRITING TO A SINGLE REGISTER WITH THE "WRITE BYTE" PROTOCOL
1
S
7
SLAVE ADDRESS
1
0
1
A
8
REGISTER POINTER
1
A
8
DATA
1
A
1
P
NUMBER OF BITS
R/W
B. WRITING TO MULTIPLE REGISTERS
1
S
7
SLAVE ADDRESS
1
0
1
A
8
REGISTER POINTER X
1
A
8
DATA X
1
A
8
DATA X+1
1
A
NUMBER OF BITS
R/W
8
DATA X+n-1
1
A
8
DATA X+n
1
A
P
NUMBER OF BITS
Figure 14. Writing to the MAX8939/MAX8939A/MAX8939B
SMBus is a trademark of Intel Corp.
26
Maxim Integrated
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