参数资料
型号: MAX9224ETI+T
厂商: Maxim Integrated Products
文件页数: 10/15页
文件大小: 0K
描述: IC DESERIALIZER LP 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 串行器/解串器
数据速率: 220Mbps
输入类型: 并联
输出类型: 并联
输入数: 1
输出数: 22
电源电压: 2.375 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
MAX9223/MAX9224
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS—MAX9223
(VDD = +2.375V to +3.465V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +2.5V, TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PCLKIN INPUT REQUIREMENTS (Figure 3)
Input Rise Time
tR
2ns
Input Fall Time
tF
2ns
PCLKIN Period
tP
100
200
ns
High-Level Pulse Width
tPWH
0.3 x tP
0.7 x tP
ns
Low-Level Pulse Width
tPWL
0.3 x tP
0.7 x tP
ns
Setup Time
tS
3ns
Hold Time
tH
1ns
AC ELECTRICAL CHARACTERISTICS—MAX9224
(VDD = VDDO = +2.375V to +3.465V, CL = 5pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = VDDO =
+2.5V, TA = +25°C.) (Notes 3, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PCLKOUT Period
tP
Figure 4
100
200
ns
High-Level Pulse Width
tPWH
Figure 4
0.4 x tP
0.6 x tP
ns
Low-Level Pulse Width
tPWL
Figure 4
0.4 x tP
0.6 x tP
ns
Data Valid Before PCLKOUT
tVB
Figure 4
5
ns
Data Valid After PCLKOUT
tVA
Figure 4
5
ns
SERIALIZER AND DESERIALIZER LINK
tPU1
From VDD = VDDO = 2.375V when supplies
are ramping up
6144 x
tP
Power-Up Time
tPU2
From
PWRDN low to high
4096 x
tP
ns
Power-Down Time
tPWRDN
From
PWRDN high to low
2.8
10
s
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +85°C.
Note 3: Parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 4: ITOT = IDD + IDDO.
Note 5: CL includes probe and test jig capacitance.
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