参数资料
型号: MAX9224ETI+T
厂商: Maxim Integrated Products
文件页数: 15/15页
文件大小: 0K
描述: IC DESERIALIZER LP 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 串行器/解串器
数据速率: 220Mbps
输入类型: 并联
输出类型: 并联
输入数: 1
输出数: 22
电源电压: 2.375 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
LCDS
The MAX9223/MAX9224 use a proprietary multilevel
LCDS interface. Figure 5 provides a representation of
the data and clock in the multilevel LCDS interface.
This interface offers advantages over other chipsets,
such as requiring only one differential pair as the trans-
mission medium, the inherently aligned data and clock,
and much smaller current levels than the 4mA typically
found in traditional LVDS interfaces.
MAX9223/MAX9224 Handshaking
The handshaking function of the MAX9223/MAX9224
provides bidirectional communication between the two
devices in case a word boundary error is detected. Prior
to data transmission, the MAX9223 serializer adds
boundary bits (OH) to the end of the latched word.
These boundary bits are the inverse of the last bit of the
latched word. During data transmission, the MAX9224
deserializer continuously monitors the state of the
boundary bits of each word. If a word boundary error is
detected, the serial link is pulled up to VDD and the
MAX9224 powers down. The MAX9223 detects the
pullup of the serial link and powers down for 1.0s. After
1.0s, the MAX9223 powers up, causing the power-up
of the MAX9224. Then the word boundary is reestab-
lished, and data transfer resumes. The handshaking
function is disabled when PWRDN is pulled low.
MAX9223/MAX9224
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
_______________________________________________________________________________________
9
MAX9223 Functional Diagram
TIMING
AND
CONTROL
PARALLEL
TO
SERIAL
DLL
PWRDN
LATCH
INPUT
PCLKIN
DIN[21:0]
SDO+
SDO-
MAX9223
MAX9224 Functional Diagram
DOUT[21:0]
TIMING AND CONTROL
OUTPUT
LATCH
PCLKOUT
SERIAL
TO
PARALLEL
SDI+
SDI-
MAX9224
Detailed Description
The MAX9223 serializer operates at a 5MHz to 10MHz
parallel clock frequency, serializing 22 bits of parallel
input data DIN[21:0] in each cycle of the parallel clock.
DIN[21:0] are latched on the rising edge of PCLKIN.
The data and internally generated serial clock are com-
bined and transmitted through SDO+/SDO- using multi-
level LCDS. The MAX9224 deserializer receives the
LCDS signal on SDI+/SDI-. The deserialized data and
recovered parallel clock are available at DOUT[21:0]
and PCLKOUT. Output data is valid on the rising edge
of PCLKOUT.
The first bit (G) is internally grounded and transmitted
first. Bit 0 (DIN[0]) is the first valid data bit. Boundary
bits OH are used by the MAX9224 deserializer to identi-
fy the word boundary and are the inverse polarity of
data bit 21 (DIN[21]). Therefore, at least one level tran-
sition is guaranteed in one word. The clock is recov-
ered from the serial input.
G
0
1
2
3
4
5
6
7
8
9
1011
1213
1415
1617
1819
2021
OH OH
Serial word format:
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