Detailed Description
The MAX9312/MAX9314 are low-skew, dual 1-to-5 differ-
ential drivers designed for clock and data distribution.
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.25V to +3.8V supply
range, allowing high-performance clock or data distribu-
tion in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.25V to -3.8V supply.
The differential inputs can be configured to accept sin-
gle-ended inputs when operating at approximately VCC -
VEE = 3.0V to 3.8V for the MAX9312 or VCC - VEE = 2.7V
to 3.8V for the MAX9314. This is accomplished by con-
necting the on-chip reference voltage, VBB, to an input
as a reference. For example, the differential CLKA, CLKA
input is converted to a noninverting, single-ended input
by connecting VBB to CLKA and connecting the single-
ended input to CLKA. Similarly, an inverting input is
obtained by connecting VBB to CLKA and connecting
the single-ended input to CLKA. With a differential input
configured as single ended (using VBB), the single-
ended input can be driven to VCC and VEE or with a sin-
gle-ended LVPECL/LVECL signal.
When a differential input is configured as a single-ended
input (using VBB), the approximate supply range is VCC -
VEE = 3.0V to 3.8V for the MAX9312 and VCC - VEE =
2.7V to 3.8V for the MAX9314. This is because one of the
inputs must be VEE + 1.2V or higher for proper operation
of the input stage. VBB must be at least VEE + 1.2V
because it becomes the high-level input when the other
(single-ended) input swings below it. Therefore, mini-
mum VBB = VEE + 1.2V.
The minimum VBB output for the MAX9312 is VCC -
1.525V and the minimum VBB output for the MAX9314 is
VCC - 1.38V. Substituting the minimum VBB output for
each device into VBB = VEE + 1.2V results in a minimum
supply of 2.725V for the MAX9312 and 2.58V for the
MAX9314. Rounding up to standard supplies gives the
single-ended operating supply ranges of VCC - VEE =
3.0V to 3.8V for the MAX9312 and VCC - VEE = 2.7V to
3.8V for the MAX9314.
When using the VBB reference output, bypass it with a
0.01F ceramic capacitor to VCC. If the VBB reference is
not used, it can be left open. The VBB reference can
source or sink 0.5mA, which is sufficient to drive two
inputs. Use VBB only for inputs that are on the same
device as the VBB reference.
The maximum magnitude of the differential input from
CLK_ to CLK_ is 3.0V or VCC - VEE, whichever is less.
This limit also applies to the difference between any ref-
erence voltage input and a single-ended input.
The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting inputs (CLKA and CLKB) are biased with a
75k
pullup to VCC and a 75k pulldown to VEE. The
noninverting inputs (CLKA and CLKB) are biased with a
75k
pulldown to VEE.
Specifications for the high and low voltages of a differen-
tial input (VIHD and VILD) and the differential input volt-
age (VIHD - VILD) apply simultaneously (VILD cannot be
higher than VIHD).
Output levels are referenced to VCC and are considered
LVPECL or LVECL, depending on the level of the VCC
supply. With VCC connected to a positive supply and
VEE connected to GND, the outputs are LVPECL. The
outputs are LVECL when VCC is connected to GND and
VEE is connected to a negative supply.
A single-ended input of at least VBB ±95mV or a differen-
tial input of at least 95mV switches the outputs to the
VOH and VOL levels specified in the DC Electrical
Characteristics table.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1F and 0.01F capacitors in parallel as close
to the device as possible, with the 0.01F value capaci-
tor closest to the device. Use multiple parallel vias for
low inductance. When using the VBB reference output,
bypass it with a 0.01F ceramic capacitor to VCC (if the
VBB reference is not used, it can be left open).
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9312/MAX9314.
Connect each signal of a differential input or output to a
50
characteristic impedance trace. Minimize the num-
ber of vias to prevent impedance discontinuities. Reduce
reflections by maintaining the 50
characteristic imped-
ance through connectors and across cables. Reduce
skew within a differential pair by matching the electrical
length of the traces.
Output Termination
Terminate outputs through 50
to VCC - 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if QA0 is used as a single-ended
output, terminate both QA0 and QA0.
MAX9312/MAX9314
Dual 1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
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