参数资料
型号: MAX9767ETJ+
厂商: Maxim Integrated Products
文件页数: 13/33页
文件大小: 0K
描述: IC AMP AUDIO .75W STER AB 32TQFN
标准包装: 60
类型: AB 类
输出类型: 2 通道(立体声)
在某负载时最大输出功率 x 通道数量: 750mW x 2 @ 4 欧姆
电源电压: 2.7 V ~ 5.5 V
特点: 消除爆音,麦克风,静音,短路保护和热保护,关机
安装类型: 表面贴装
供应商设备封装: 32-TQFN-EP(5x5)
封装/外壳: 32-WFQFN 裸露焊盘
包装: 管件
MAX9765/MAX9766/MAX9767
750mW Audio Amplifiers with Headphone Amp,
Microphone Preamp, and Input Mux
20
______________________________________________________________________________________
Write Data Format
There are three registers that configure the
MAX9765/MAX9766: the MUTE register, SHDN register,
and control register. In write data mode (R/W = 0), the
register address and data byte follow the device
address (Figure 7).
MUTE Register
The MUTE register (01hex) is a read/write register that
sets the MUTE status of the device. Bit 3 (MUTEL) of
the MUTE register controls the left channel, bit 4
(MUTER) controls the right channel. A logic high mutes
the respective channel, a logic low brings the channel
out of mute.
SHDN Register
The SHDN register (02hex) is a read/write register that
controls the power-up state of the device. A logic high
in bit 0 of the SHDN register shuts down the device; a
logic low turns on the device. A logic high is required in
bits 2 to 7 to reset all registers to their default register
settings.
Control Register
The control register (03hex) is a read/write register that
determines the device configuration. Bit 1 (IN1/IN2)
controls the input multiplexer, a logic high selects input
1, a logic low selects input 2. Bit 2 (HPS_EN) controls
the headphone sensing. A logic low configures the
device in automatic headphone detection mode. A
logic high disables the HPS input. Bit 3 (INT/EXT) con-
trols the microphone amplifier inputs. A logic low
selects differential (internal) input mode. A logic high
selects single-ended (external) input mode. Bit 4
(SPKR/HP) selects the amplifier operating mode when
SCL
SDA
STOP
START
SCL
SDA
ILLEGAL
STOP
START
LEGAL STOP CONDITION
ILLEGAL EARLY STOP CONDITION
Figure 5. Early STOP Condition
S
A6A5A4A3A2A1A0
R/W
Figure 6. Slave Address Byte Definition
ADD CONNECTION
I
2C ADDRESS
GND
100 1000
VDD
100 1001
SDA
100 1010
SCL
100 1011
Table 2. I2C Slave Addresses
REGISTER
ADDRESS
0000 0001
BIT
NAME
VALUE
DESCRIPTION
7
X
Don’t Care
6
X
Don’t Care
5
X
Don’t Care
0*
Unmute right channel
4
MUTER
1
Mute right channel
0*
Unmute left channel
3
MUTEL
1
Mute left channel
2
X
Don’t Care
1
X
Don’t Care
0
X
Don’t Care
Table 3. MUTE Register Format
*Default state.
HPS_D BIT
HPS
SPKR/
HP BIT
MODE
0
X
BTL
01
X
SE
1
X
0
BTL
1X
1
SE
Table 1. HPS Setting (MAX9765/MAX9766)
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