Click-and-Pop Suppression
In conventional single-supply headphone amplifiers, the
output-coupling capacitor is a major contributor of audi-
ble clicks and pops. Upon startup, the amplifier charges
the coupling capacitor to its bias voltage, typically half the
supply. Likewise, during shutdown, the capacitor is dis-
charged to GND. This results in a DC shift across the
capacitor, which, in turn, appears as an audible transient
at the speaker. Since the MAX9775/MAX9776 headphone
amplifier does not require output-coupling capacitors, this
problem does not arise.
In most applications, the output of the preamplifier dri-
ving the MAX9775/MAX9776 has a DC bias of typically
half the supply. During startup, the input-coupling
capacitor is charged to the preamplifier’s DC bias volt-
age, resulting in a DC shift across the capacitor and an
audible click/pop. An internal delay of 30ms eliminates
the click/pop caused by the input filter.
Shutdown
The MAX9775/MAX9776 feature a 0.1A hard shutdown
mode that reduces power consumption to extend battery
life and a soft shutdown where current consumption is
typically 8.5A. Hard shutdown is controlled by connect-
ing the SHDN pin to GND, disabling the amplifiers, bias
circuitry, charge pump, and I2C. In shutdown, the head-
phone amplifier output impedance is 1.4k
Ω and the
speaker output impedance is 300k
Ω. Similarly, the
MAX9775/MAX9776 enter soft-shutdown when the SHDN
bit = 0 (see Table 2). The I2C interface is active and the
contents of the command register are not affected when
in soft-shutdown. This allows the master to write to the
MAX9775/MAX9776 while in shutdown. The I2C interface
is completely disabled in hardware shutdown. When the
MAX9775/MAX9776 are re-enabled the default settings
are applied (see Table 3).
I2C Interface
The MAX9775/MAX9776 feature an I2C 2-wire serial
interface consisting of a serial data line (SDA) and a
serial clock line (SCL). SDA and SCL facilitate commu-
nication between the MAX9775/MAX9776 and the mas-
ter at clock rates up to 400kHz. Figure 8 shows the
2-wire interface timing diagram. The MAX9775/
MAX9776 are receive-only slave devices relying on the
master to generate the SCL signal. The master, typical-
ly a microcontroller, generates SCL and initiates data
transfer on the bus. The MAX9775/MAX9776 cannot
write to the SDA bus except to acknowledge the receipt
of data from the master. The MAX9775/MAX9776 will
not acknowledge a read command from the master.
A master device communicates to the MAX9775/
MAX9776 by transmitting the proper address followed
by the data word. Each transmit sequence is framed by
a START (S) or REPEATED START (Sr) condition and a
STOP (P) condition. Each word transmitted over the
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
The MAX9775/MAX9776 SDA line operates as both an
input and an open-drain output. A pullup resistor,
greater than 500
Ω, is required on the SDA bus. The
MAX9775/MAX9776 SCL line operates as an input only.
A pullup resistor (greater than 500
Ω) is required on
SCL if there are multiple masters on the bus or if the
master in a single-master system has an open-drain
SCL output. Series resistors in line with SDA and SCL
are optional. Series resistors protect the digital inputs of
the MAX9775/MAX9776 from high-voltage spikes on
the bus lines, and minimize crosstalk and undershoot of
the bus signals.
MAX9775/MAX9776
2 x 1.5W, Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
______________________________________________________________________________________
25
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START
CONDITION
START
CONDITION
tHD, STA
tSU, STA
tHD, STA
tSP
tBUF
tSU, STO
tLOW
tSU, DAT
tHD, DAT
tHIGH
tR
tF
Figure 8. 2-Wire Serial-Interface Timing Diagram