参数资料
型号: MAX9792CETI+
厂商: Maxim Integrated Products
文件页数: 12/34页
文件大小: 0K
描述: IC AMP AUDIO 2.0W STER D 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: DirectDrive®
类型: D 类
输出类型: 1-通道(单声道),带立体声耳机
在某负载时最大输出功率 x 通道数量: 3.7W x 1 @ 3 欧姆; 180mW x 2 @ 32 欧姆
电源电压: 4.5 V ~ 5.5 V
特点: 消除爆音,LDO,短路保护和热保护,关机
安装类型: 表面贴装
供应商设备封装: 28-TQFN-EP(4x4)
封装/外壳: 28-WFQFN 裸露焊盘
包装: 管件
MAX9791/MAX9792
Windows Vista-Compliant Class D Speaker
Amplifiers with DirectDrive Headphone Amplifiers
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VAVDD = VPVDD = VHPVDD = 5V, VGND = VPGND = VCPGND = 0, ILDO_OUT = 0, CLDO = 2F (CLDO = 4F for 1.8V LDO option),
C1 = C2 = 1F. RL = ∞, unless otherwise specified. RIN1 = 20k (AVSPKR = 12dB), RIN2 = 40.2k (AVHP = 0dB), CIN1 = 470nF,
CIN2 =CCOM = 1F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage
(AVDD, PVDD, HPVDD to GND)........................-0.3V to +6.0V
(AVDD to PVDD) .............................................................±0.3V
GND to PGND, CPGND ......................................................±0.3V
CPVSS, C1N to GND ............................................-6.0V to + 0.3V
HPL, HPR to CPVSS ...........................................-0.3V to lower of
(HPVDD - CPVSS + 0.3V) and +9V
HPL, HPR to HPVDD..................................+0.3V to the higher of
(CPVSS - HPVDD - 0.3V) and -9V
COM, SENSE........................................................-0.3V to + 0.3V
Any Other Pin ..........................................-0.3V to (AVDD + 0.3V)
Duration of Short Circuit between OUT_+, OUT_- and GND,
PGND, AVDD, or PVDD..........................................Continuous
Duration of Short Circuit between LDO_OUT and AVDD,
GND (Note 1) .........................................................Continuous
Duration of Short Circuit between HPR, HPL and
GND .......................................................................Continuous
Continuous Current (PVDD, OUT_+, OUT_-, PGND)............1.7A
Continuous Current (C1N, C1P, CPVSS, AVDD, HPVDD,
LDO_OUT, HPR, HPL) ..................................................850mA
Continuous Input Current (All Other Pins) ........................±20mA
Continuous Power Dissipation (TA = +70°C)
28-Pin Thin QFN Single-Layer Board (derate 20.8mW/°C
above +70°C)..........................................................1667mW
Junction-to-Ambient Thermal Resistance (
θJA)
(Note 2) .....................................................................40°C/W
Junction-to-Case Thermal Resistance (
θJC)
(Note 2) ....................................................................2.7°C/W
28-Pin Thin QFN Multilayer Board (derate 28.6mW/°C
above +70°C)..........................................................2286mW
Junction-to-Ambient Thermal Resistance (
θJA)
(Note 2) .....................................................................35°C/W
Junction-to-Case Thermal Resistance (
θJC)
(Note 2) ....................................................................2.7°C/W
ESD Protection, Human Body Model ...................................±2kV
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL
Supply Voltage
VAVDD,
VPVDD
Guaranteed by PSRR test (Note 4)
2.7
5.5
V
Headphone Supply Voltage
VHPVDD
Guaranteed by PSRR test
2.7
5.5
V
Undervoltage Lockout
UVLO
2.65
V
SPKR_EN
HP_EN
LDO_EN
1
0
1
250
400
A
1
0
4.4
6
0
10.5
15
MAX9791
0
1
0
14.4
21
mA
1
0
1
250
400
A
1
0
4.4
6
0
10.5
18
Quiescent Current
IAVDD +
IPVD +
IHPVDD
MAX9792
0
1
0
14.4
24
mA
Shutdown Current
ISHDN
SPKR_EN = 1.8V
3.3
7..3
A
Bias Voltage
VBIAS
HP_INR, HP_INL, SPKR_INR, SPKR_INL
0
V
Note 1: If short is present at power-up.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
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