参数资料
型号: MAX9875ERP+T
厂商: Maxim Integrated Products
文件页数: 13/30页
文件大小: 0K
描述: IC AUDIO SUBSYSTEM 20UCSP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: DirectDrive®
类型: D 类
输出类型: 1-通道(单声道),带立体声耳机
在某负载时最大输出功率 x 通道数量: 825mW x 1 @ 4 欧姆; 53mW x 2 @ 16 欧姆
电源电压: 2.7 V ~ 5.25 V
特点: 消除爆音,差分输入,I²C,静音,短路和热保护,关机,音量控制
安装类型: 表面贴装
供应商设备封装: 20-UCSP
封装/外壳: 20-WFBGA,CSPBGA
包装: 带卷 (TR)
MAX9875
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
20
______________________________________________________________________________________
I2C Register Description
Zero-Crossing Detection (ZCD)
Zero-crossing detection limits distortion in the output
signal during volume transitions by delaying the transi-
tion until the mixer output crosses the internal bias volt-
age. A timeout period (typically 60ms) forces the
volume transition if the mixer output signal does not
cross the bias voltage.
1 = Zero-crossing detection is enabled.
0 = Zero-crossing detection is disabled.
Differential Input Configuration (IN_)
The inputs INA_ and INB_ can be configured for mono
differential or stereo single-ended operation.
1 = IN__ is configured as a mono differential input with
IN_2 as the positive and IN_1 as the negative input.
0 = IN__ is configured as a stereo single-ended input
with IN_2 as the right and IN_1 as the left input.
Preamplifier Gain (PGAIN_)
The preamplifier gain of INA_ and INB_ can be pro-
grammed by writing to PGAIN_.
00 = 0dB
01 = +9dB
10 = +20dB
11 = Reserved
The MAX9875 is controlled through five I2C program-
mable registers. Table 1 shows the MAX9875’s com-
plete register map. Tables 2, 3, and 5 show the
individual registers.
I2C Address
The slave address of the MAX9875 is 1001101R/(W).
Table 1. Register Map
REGISTER
ADDRESS
POR STATE
B7
B6
B5
B4
B3
B2
B1
B0
Input Mode
Control
0x00
0x40
0
ZCD
INA
INB
PGAINA
PGAINB
Speaker
Volume
Control
0x01
0x00
0
SVOL (Table 4)
Left
Headphone
Volume
Control
0x02
0x00
0
HPLVOL (Table 4)
Right
Headphone
Volume
Control
0x03
0x00
0
HPRVOL (Table 4)
Output Mode
Control
0x04
0x49
SHDN
0
OSC (Table 6)
OUTMODE (Table 7)
Table 2. Input Mode Control
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
0x00
0
ZCD
INA
INB
PGAINA
PGAINB
I2C Interface
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