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| 型号： | MAX9947ETE+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 4/17页 |
| 文件大小： | 0K |
| 描述： | TXRX AISG INTEGRATED 16TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 频率： | 2.176MHz |
| 数据传输率 - 最大： | 115.2kbps |
| 调制或协议： | OOK |
| 应用： | AISG |
| 功率 - 输出： | 12dBm |
| 电源电压： | 3 V ~ 5.5 V |
| 数据接口： | PCB，表面贴装 |
| 存储容量： | * |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
AISG Integrated Transceiver
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 5V, V L = 3.3V, TXOUT connected with 50 I to RXIN, 4.1k I resistor between BIAS and RES, 10k I resistor between RES and
GND, 1k I resistor between SYNCOUT and V CC , T A = T MIN to T MAX , unless otherwise specified. XTAL frequency 8.704MHz ±30ppm.
Typical values are at T A = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
SWITCHING CHARACTERISTICS
RXIN to RXOUT, V DIRMD1 = V DIRMD2 = 0V
8.9
11
Receiver Propagation Delay
t RX
RXIN to RXOUT, V DIRMD1 = 3.3V,
V DIRMD2 = 0V (38.4kbps), V DIRMD1 = 0V,
5.5
11
F s
V DIRMD2 = 3.3V (115.2kbps)
Receiver Output Rise and
Fall Time
Transmitter Propagation Delay
DIR to RXOUT Delay (Note 8)
t R , t F
t TX
t DIR, SKEW
10% to 90%, R L = 1k I , C L = 10pF
TXIN to TXOUT
270
20
5
ns
F s
ns
V DIRMD1 = V DIRMD2 = 0V (9.6kbps)
1667
Direction Duration High
t DIR, HIGH
V DIRMD1 = 3.3V, V DIRMD2 = 0V (38.4kbps)
417
F s
V DIRMD1 = 0V, V DIRMD 2 = 3.3V (115.2kbps)
137
Receiver Output Data
Duty-Cycle Variation
D DC
RXIN fed by an OOK
2.176MHz sinusoidal
signal with 50% duty
cycle (Note 9)
RXIN = 0dBm
RXIN = -10dBm
-7.5
+2
Q 10
Q 10
%
Note
Note
Note
Note
Note
Note
2:
3:
4.
5:
6:
7:
All devices are 100% production tested at T A = +25°C. Specification over temperature limits are guaranteed by design.
Defined as D V RXIN / D V CC at DC.
Defined as D V TXOUT / D V CC at DC.
Guaranteed by design.
See the Transmission Output Power section for external resistor values.
Guaranteed by design with a recommended 470pF capacitor between RXIN and ground. Measurements above 150MHz
are determined by setup.
Note 8: See Figure 1.
Note 9: Q 2μs envelope rise/fall.
4
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