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参数资料
| 型号： | MAX9989ETP+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 3/12页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER LO 20-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | LO 缓冲器/分路器 |
| 频率： | 700MHz ~ 1.1GHz |
| RF 型： | 手机，GSM，DCS，PCS，UMTS |
| 次要属性： | 40dB 反向隔离 |
| 封装/外壳： | 20-WQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
+14dBm to +20dBm LO Buffers
with ±1dB Variation
AC ELECTRICAL CHARACTERISTICS — MAX9989
( Typical Application Circuit , V CC = 4.75V to 5.25V, 50 ? environment, +4dBm < P IN < +10dBm, 700MHz < f IN < 1100MHz,
T A = -40 ° C to +85 ° C, unless otherwise noted. Typical specifications are for V CC = 5.0V, P IN = +7dBm, f IN = 900MHz, and
T A = +25 ° C, unless otherwise noted.) (Note 1)
PARAMETER
Operating Frequency
SYMBOL
f
CONDITIONS
MIN
700
TYP
MAX
1100
UNITS
MHz
Low power setting, P IN = +4dBm
(see Table 1 for resistor values)
Nominal power setting,
14.3
Output Power
P OUTLO
+4dBm < P IN < +10dBm
4.75V < V CC < 5.25V
17.3
±0.8
dBm
-40 ° C < T A < +85 ° C (R2 – R5 not installed)
High power setting, P IN = +10dBm
(see Table 1 for resistor values)
19.7
Output Power (PLL Driver)
Input VSWR
Output VSWR
P OUTPLL
VSWR IN
VSWR OUT
3.7
1.2:1
1.7:1
dBm
Output-Noise Power Density
OUTLO to RFIN Isolation
P NOISE
S12
V CC = 5.0V, ±100MHz offset
(R2 – R5 not installed)
V CC = 5.0V, nominal power setting
(R2 – R5 not installed)
-152
48
dBm/Hz
dB
AC ELECTRICAL CHARACTERISTICS — MAX9990
( Typical Application Circuit , V CC = 4.75V to 5.25V, 50 ? environment, +6dBm < P IN < +12dBm, 1500MHz < f IN < 2200MHz, and
T A = -40 ° C to +85 ° C, unless otherwise noted. Typical specifications are for V CC = 5.0V, P IN = +9dBm, f IN = 1800MHz, and
T A = +25 ° C, unless otherwise noted.) (Note 1)
PARAMETER
Operating Frequency
SYMBOL
f
CONDITIONS
MIN
1500
TYP
MAX
2200
UNITS
MHz
Low power setting, P IN = +6dBm
(see Table 1 for resistor values)
Nominal power setting,
14.2
Output Power
P OUTLO
+6dBm < P IN < +12dBm
4.75V < V CC < 5.25V
17.3
±0.8
dBm
-40 ° C < T A < +85 ° C (R2 – R5 not installed)
High power setting, P IN = +12dBm
(see Table 1 for resistor values)
19.5
Output Power (PLL Driver)
Input VSWR
Output VSWR
P OUTPLL
VSWR IN
VSWR OUT
3.6
1.5:1
1.4:1
dBm
Output-Noise Power Density
OUTLO to RFIN Isolation
P NOISE
S12
V CC = 5.0V, ±100MHz offset
V CC = 5.0V, nominal power setting
(R2 – R5 not installed)
-152
49
dBm/Hz
dB
Note 1: Devices are 100% DC screened and AC production tested for functionality. Data sheet typical specifications are derived
from the average of 30 units from a typical lot, and are tested under the conditions specified for the typical specifications.
Note 2: DC current limits at -40 ° C are guaranteed by design and characterization.
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