参数资料
型号: MAXQ3120-FFN+
厂商: Maxim Integrated Products
文件页数: 30/33页
文件大小: 0K
描述: IC MCU 32KB FLASH 80-MQFP
标准包装: 66
系列: MAXQ®
核心处理器: RISC
芯体尺寸: 16-位
速度: 8MHz
连通性: UART/USART
外围设备: LCD,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 2.8 V ~ 3.6 V
数据转换器: A/D 2x16b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 80-BQFP
包装: 托盘
MAXQ3120
High-Precision ADC
Mixed-Signal Microcontroller
6
_____________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
22, 38,
60, 74
DVDD
Digital Supply Voltage (+3.3V)
19, 37, 43,
59, 75
DGND
Digital Ground
44
AVDD
Analog Supply Voltage
52
AGND
Analog Ground
12
VLCD
LCD Bias-Control Voltage. Highest LCD drive voltage used in all bias modes. This pin must be
connected to an external supply when using the LCD display controller.
13
VLCD1
LCD Bias, Voltage 1. Next highest LCD drive voltage, used in 1/2 and 1/3 LCD bias modes. An internal
resistor-divider sets the voltage at this pin. External resistors and capacitors can be used to change
LCD voltage or drive capability at this pin. This pin must be shunted externally to VLCD2 when using 1/2
bias mode.
14
VLCD2
LCD Bias, Voltage 2. Third highest LCD drive voltage, used in 1/3 LCD bias mode only. An internal
resistor-divider sets the voltage at this pin. External resistors and capacitors can be used to change
LCD voltage or drive capability at this pin. This pin must be shunted externally to VLCD1 when using
1/2 bias mode.
15
VADJ
LCD Adjustment Voltage. Lowest LCD drive voltage, used in all bias modes. Connect to DGND
through an external resistor to provide external control of the LCD contrast. Leave disconnected for
internal contrast adjustment.
63
RESET
Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this is low and begins
executing from the reset vector when released. The pin includes a pullup current source and should be
driven by an open-drain, external source capable of sinking in excess of 2mA. This pin is driven low as
an output when an internal reset condition occurs.
20
HFXIN
High-Frequency Crystal Input. Connect an external crystal between HFXIN and HFXOUT to generate
the high-frequency system clock. HFXIN and HFXOUT contain integral 16pF load capacitors, so no
external capacitor is required.
21
HFXOUT
High-Frequency Crystal Output. Connect an external crystal between HFXIN and HFXOUT to
generate the high-frequency system clock. HFXIN and HFXOUT contain integral 16pF load capacitors,
so no external capacitor is required.
53
VBAT
Digital Battery-Backup Supply. This supply provides an optional battery backup for the RTC when
DVDD power is removed. If this supply is not provided, all functions of the device operate as normal,
but the RTC is cleared upon power-on reset (POR).
61
32KIN
32kHz Crystal Input. Connect an external, 32kHz watch crystal between 32KIN and 32KOUT to
generate the 32kHz system clock. This clock is required for the RTC to operate.
62
32KOUT
32kHz Crystal Output. Connect an external, 32kHz watch crystal between 32KIN and 32KOUT to
generate the 32kHz system clock. This clock is required for the RTC to operate.
51
VREF
Voltage Reference Input/Output. Bias voltage (+1.25V) for the ADCs. An external reference voltage
can be connected to this pin when extremely high accuracy is required.
45
AN0-
Negative Input for Sigma-Delta ADC Channel 0
46
AN0+
Positive Input for Sigma-Delta ADC Channel 0
47
AN1-
Negative Input for Sigma-Delta ADC Channel 1
48
AN1+
Positive Input for Sigma-Delta ADC Channel 1
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