参数资料
型号: MAXQ622X-0000+
厂商: Maxim Integrated Products
文件页数: 16/35页
文件大小: 0K
描述: IC MCU 16BIT IR MOD BARE DIE
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: MAXQ®
核心处理器: RISC
芯体尺寸: 16-位
速度: 12MHz
连通性: I²C,SPI,UART/USART,USB
外围设备: 欠压检测/复位,红外线,电源故障,POR,WDT
输入/输出数: 56
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
RAM 容量: 6K x 8
电压 - 电源 (Vcc/Vdd): 1.7 V ~ 3.6 V
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 模具
包装: 托盘
配用: MAXQ622-KIT#-ND - EVALUATION KIT FOR MAXQ622
其它名称: 90-M6900+D01
23
Maxim Integrated
16-Bit Microcontrollers with
Infrared Module and Optional USB
MAXQ612/MAXQ622
ROM consists of subroutines that can be called from
application software. These include the following:
In-system programming (bootstrap loader) using
JTAG interface
In-circuit debug routines
Test routines (internal memory tests, memory loader,
etc.)
User-callable routines for in-application flash memory
programming and fast table lookup
Following any reset, execution begins in the utility ROM.
The ROM software determines whether the program
execution should immediately jump to location 0000h,
the start of system code, or to one of the special rou-
tines mentioned. Routines within the utility ROM are user
accessible and can be called as subroutines by the
application software. More information on the utility ROM
functions is contained in the MAXQ622 User’s Guide.
Some applications require protection against unau-
thorized viewing of program code memory. For these
applications, access to in-system programming, in-
application programming, or in-circuit debugging func-
tions is prohibited until a password has been supplied.
The password is defined as the 16 words of physical
program memory at addresses 0010h to 001Fh.
Three password locks protect three different program
memory segments. When the PWL is set to one (power-
on reset default) and the contents of the memory at
addresses 0010h to 001Fh are any value other than FFh
or 00h, the password is required to access the utility
ROM, including in-circuit debug and in-system program-
ming routines that allow reading or writing of internal
memory. When PWL is cleared to zero, these utilities are
fully accessible without password. The PWLS bit uses a
password that is at ULDR + 0010 to ULDR + 001F, and
the PWLL uses a password at UAPP + 0010 to UAPP +
001F. The password is automatically set to all ones fol-
lowing a mass erase.
Watchdog Timer
The internal watchdog timer greatly increases system
reliability. The timer resets the device if software execu-
tion is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the applica-
tion software. If software is operating correctly, the coun-
ter is periodically reset and never reaches its maximum
count. However, if software operation is interrupted,
the timer does not reset, triggering a system reset and
optionally a watchdog timer interrupt. This protects the
system against electrical noise or electrostatic discharge
(ESD) upsets that could cause uncontrolled processor
operation. The internal watchdog timer is an upgrade to
older designs with external watchdog devices, reducing
system cost and simultaneously increasing reliability.
The watchdog timer functions as the source of both the
watchdog timer timeout and the watchdog timer reset.
The timeout period can be programmed in a range of
215 to 224 system clock cycles. An interrupt is gener-
ated when the timeout period expires if the interrupt
is enabled. All watchdog timer resets follow the pro-
grammed interrupt timeouts by 512 system clock cycles.
If the watchdog timer is not restarted for another full
interval in this time period, a system reset occurs when
the reset timeout expires.
IR Carrier Generation
and Modulation Timer
The dedicated IR timer/counter module simplifies low-
speed infrared (IR) communication. The IR timer imple-
ments two pins (IRTX and IRRX) for supporting IR
transmit and receive, respectively. The IRTX pin has no
corresponding port pin designation, so the standard
PD, PO, and PI port control status bits are not present.
However, the IRTX pin output can be manipulated high
or low using the PWCN.IRTXOUT and PWCN.IRTXOE
bits when the IR timer is not enabled (i.e., IREN = 0).
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
WD[1:0]
WATCHDOG CLOCK
WATCHDOG INTERRUPT TIMEOUT
WATCHDOG RESET AFTER
WATCHDOG INTERRUPT (s)
00
Sysclk/215
2.7ms
42.7
01
Sysclk/218
21.9ms
42.7
10
Sysclk/221
174.7ms
42.7
11
Sysclk/224
1.4s
42.7
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