参数资料
型号: MAXQ7665BATM+
厂商: Maxim Integrated Products
文件页数: 9/47页
文件大小: 0K
描述: IC MCU-BASED DAS 16BIT 48-TQFN
标准包装: 43
系列: MAXQ®
核心处理器: RISC
芯体尺寸: 16-位
速度: 8MHz
连通性: CAN,LIN,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 8
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
RAM 容量: 256 x 16
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.25 V
数据转换器: A/D 8x12b,D/A 1x12b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 48-TQFN 裸露焊盘
包装: 管件
MAXQ7665A–MAXQ7665D
16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
______________________________________________________________________________________
17
Pin Description (continued)
PIN
NAME
FUNCTION
33
P0.1/TMS
Port 0 Data 1/JTAG Test Mode Select. P0.1 is a general-purpose digital I/O with interrupt/wake-
up capability. TMS is the JTAG test mode, select input.
34
P0.2/TDI
Port 0 Data 2/JTAG Serial Test Data Input. P0.2 is a general-purpose digital I/O with
interrupt/wake-up capability. TDI is the JTAG serial test, data input.
35
P0.3/TCK
Port 0 Data 3/JTAG Serial Test Clock Input. P0.3 is a general-purpose digital I/O with
interrupt/wake-up capability. TCK is the JTAG serial test, clock input.
36
P0.4/ADCCNV
Port 0 Data 4/ADC Start Conversion Control. P0.4 is a general-purpose digital I/O. ADCCNV is
firmware configurable for a rising or falling edge start/convert to trigger ADC conversions.
37
P0.5/DACLOAD
Port 0 Data 5/DAC Data Register Load/Update Input. P0.5 is a general-purpose digital I/O with
interrupt/wake-up capability. DACLOAD is firmware configurable for a rising or falling edge to
update the DACOUT register.
38
REGEN
Active-Low Linear Regulator Enable Input. Connect REGEN to GNDIO to enable the linear
regulator. Connect to DVDDIO to disable the linear regulator.
40
DVDD
Digital Supply Voltage. DVDD supplies the internal digital core and flash memory. DVDD is
internally connected to the output of the internal 3.3V linear regulator. Disable the internal
regulator to connect DVDD to an external supply. When using the on-chip linear regulator, bypass
DVDD to DGND with a 4.7F ±20% capacitor with a maximum ESR of 0.5
. In addition, bypass
DVDD with a 0.1F capacitor. Place both bypass capacitors as close as possible to the device.
41
RESET
Reset Input and Output. Active-low open-drain input/output with internal 360k
pullup to DVDD.
Drive low to reset the C. RESET is low during power-up reset and during DVDD brownout
conditions.
42
XOUT
High-Frequency Crystal Output. Connect an external crystal to XIN and XOUT for normal
operation. Leave XOUT unconnected if XIN is driven with an external clock source. XOUT is not
driven when using the internal RC oscillator.
43
XIN
High-Frequency Crystal Input. Connect an external crystal or resonator to XIN and XOUT for
normal operation, or drive XIN with an external clock source. XIN is not driven when using the
internal RC oscillator.
44
AVDD
Analog Supply Voltage Input. Connect AVDD to a +5V supply. Bypass AVDD to AGND with a
0.1F capacitor placed as close as possible to the device.
45
AIN15
Analog Input Channel 15. AIN15 is multiplexed to the PGA as a differential input with AIN14.
46
AIN14
Analog Input Channel 14. AIN14 is multiplexed to the PGA as a differential input with AIN15.
47
AIN13
Analog Input Channel 13. AIN13 is multiplexed to the PGA as a differential input with AIN12.
48
AIN12
Analog Input Channel 12. AIN12 is multiplexed to the PGA as a differential input with AIN13.
EP
Exposed Pad. EP is internally connected to AGND. Connect EP to AGND externally.
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