参数资料
型号: MAXQ7670AATL/V+T
厂商: Maxim Integrated Products
文件页数: 11/38页
文件大小: 0K
描述: IC MCU W/12BIT ADC 40TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: MAXQ®
核心处理器: RISC
芯体尺寸: 16-位
速度: 16MHz
连通性: CAN,SPI
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 7
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
RAM 容量: 1K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 40-WFQFN 裸露焊盘
包装: 带卷 (TR)
MAXQ7670A
Microcontroller with 12-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________
19
The MAXQ7670A ADC uses a fully differential SAR con-
version technique and an integrated T/H (track and
hold) block to convert voltage signals into a 12-bit digi-
tal result. Both single-ended and differential configura-
tions are implemented using an analog input channel
multiplexer that supports 8 single-ended or 4 differen-
tial channels.
In single-ended mode, the mux selects from either of
the ground-referenced analog inputs AIN0–AIN7. In dif-
ferential input configuration, analog inputs are selected
from the following pairs: AIN0/AIN1, AIN2/AIN3,
AIN4/AIN5, and AIN6/AIN7. Table 1 shows the single-
ended and differential input configurations possible for
the ADC mux.
Analog Input Track and Hold
A SAR conversion in the MAXQ7670A has different T/H
cycles depending on whether a gain of 1 (bypass) or a
gain of 16 (PGA enabled) is selected.
Gain = 1V/V
In gain = 1V/V, the conversion has a two-stage T/H
cycle. In track mode, a positive input capacitor con-
nects to the signal channel. A negative input capacitor
connects to the reference channel. After the T/H enters
hold mode, the difference between the signal and the
reference channel is converted to a 12-bit value. This
two-stage cycle takes 16 SARCLKs to complete.
Gain = 16V/V
In gain = 16V/V, the conversion has a three-stage T/H
cycle: amplification, ADC track, and ADC hold. First,
the PGA tracks the selected input and reference sig-
nals. The PGA amplifies the difference between the two
signals and holds the result for the next stage, ADC
track. The ADC tracks and converts the PGA result into
a 12-bit value. The SAR operation itself does not
change irrespective of the chosen gain. This three-
stage cycle takes 26.5 SARCLKs to complete. Figure 5
shows the conversion timing differences between gain
= 1V/V and gain = 16V/V.
SAR CHANNEL
SELECT
(REGISTER
ACNT[14:11])
SIGNAL CHANNEL
INTO ADC
REFERENCE
CHANNEL INTO
ADC
MEASUREMENT TYPE
0000
AIN0
AGND
Single-ended measurement on AIN0
0001
AIN1
AGND
Single-ended measurement on AIN1
0010
AIN2
AGND
Single-ended measurement on AIN2
0011
AIN3
AGND
Single-ended measurement on AIN3
0100
AIN4
AGND
Single-ended measurement on AIN4
0101
AIN5
AGND
Single-ended measurement on AIN5
0110
AIN6
AGND
Single-ended measurement on AIN6
0111
AIN7
AGND
Single-ended measurement on AIN7
1000
Reserved
1001
Reserved
1010
AIN0
AIN1
AIN0/AIN1
1011
AIN2
AIN3
AIN2/AIN3
1100
AIN4
AIN5
AIN4/AIN5
1101
AIN6
AIN7
AIN6/AIN7
1110
Reserved
1111
VCIM differential zero offset trim
Table 1. ADC Mux Input Configurations
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