参数资料
型号: MB84VD22184EA-90PBS
元件分类: 存储器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA71
封装: PLASTIC, BGA-71
文件页数: 27/64页
文件大小: 1177K
代理商: MB84VD22184EA-90PBS
MB84VD2218XEA/H/2219XEA/H-70/85/90
33
(Continued)
*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*2: This command is valid during Fast Mode.
*3: This command is valid while RESET
= VID.
*4: Valid Address is A6 to A0.
*5: This command is valid during Hi-ROM mode.
*6: The data “00h” is also acceptable.
Note : The command combinations not described in Command Definitions are illegal.
Address bits A20 to A11
= X = “H” or “L” for all address commands except for Program Address (PA) ,
Sector Address (SA) , and Bank Address (BA) .
Bus operations are defined in s DEVICE BUS OPERATION “User Bus Operations” Table.
RA
= Address of the memory location to be read.
PA
= Address of the memory location to be programmed.
Addresses are latched on the falling edge of the write pulse.
SA
= Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
BA
= Bank address (A20 to A15)
SPA
= Sector group address to be protected. Set sector group address (SPA) and (A6, A1, A0) = (0, 1, 0) .
HRA
= Address of the Hidden-ROM area.
MB84VD2218XEA/H (Top Boot Type)
Word mode : 1F8000h to 1FFFFFh
Byte mode : 3F0000h to 3FFFFFh
MB84VD2219XEA/H (Bottom Boot Type) Word mode : 000000h to 007FFFh
Byte mode : 000000h to 00FFFFh
HRBA
= Bank address of the Hidden-ROM area
MB84VD2218XEA/H (Top Boot Type)
: A20
= A19 = A18 = A17 = A16 = A15 = 1
MB84VD2219XEA/H (Bottom Boot Type) : A20
= A19 = A18 = A17 = A16 = A15 = 0
RD
= Data read from location RA during read operation.
PD
= Data to be programmed at location PA.
SD
= Sector protection verify data. Output 01h at protected sector addresses and output 00h
at unprotectedsector addresses.
The system should generate the following address patterns :
Word mode : 555h or 2AAh to addresses A10 to A0
Byte mode : AAAh or 555h to addresses A10 to A0 and A-1
Command
Sequence
Bus
Write
Cy-
cles
Req’d
First Bus
Write Cycle
Second
Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Hi-ROM Erase
*5
Word
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
HRA
30h
Byte
AAAh
555h
AAAh
555h
Hi-ROM Exit *5
Word
4
555h
AAh
2AAh
55h
(HRBA)
555h
90h XXXh 00h
Byte
AAAh
555h
(HRBA)
AAAh
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