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参数资料
| 型号： | MB8504S064AF-67 |
| 厂商： | Fujitsu Limited |
| 英文描述： | CMOS 4M×64Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4M×64位 同步动态RAM) |
| 中文描述： | 4米× 64位的CMOS同步动态随机存取存储器（SDRAM）的CMOS（4分× 64位同步动态RAM）的 |
| 文件页数： | 5/20页 |
| 文件大小： | 388K |
| 代理商： | MB8504S064AF-67 |
5
MB8504S064AF-100/-84/-67
I
SERIAL-PD INFORMATION
Note:
Any write operation must NOT be executed into the addresses of Byte 0 to Byte 127.
Some or all data stored into Byte 0 to Byte 127 may be broken.
*1. Byte 22: SDRAM Device Attributes
*2. byte 63: Checksum for Byte 0 to 62
This byte is the checksum for bytes 0 through 62. When this byte is added to the sum of bytes 0
through 62, the resulting 8-bit value is 00h.
Byte
Function Described
Hex Value
-84
80h
-100
80h
-67
80h
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 to 61
62
63
64 to 98
99 to 127
128+
Defines Number of Bytes Written into
Serial Memory at Module Manufacture
Total Number of Bytes of SPD Memory Device
Fundamental Memory Type
Number of Row Addresses
Number of Column Addresses
Number of Module Banks
Data Width
Data Width (Continuation)
Interface Type
SDRAM Cycle Time (Highest CAS Latency)
SDRAM Access from Clock (Highest CAS Latency)
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay for Back to Back Random Column
Addresses
Burst Lengths Supported
Number of Banks on Each SDRAM Device
CAS Latency
CS Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes
SDRAM Cycle Time (2nd. Highest CAS Latency)
SDRAM Access from Clock (2nd. Highest CAS Latency)
SDRAM Cycle Time (3rd. Highest CAS Latency)
SDRAM Access from Clock (3rd. Highest CAS Latency)
Minimum Row Precharge Time (t
RP
)
Row Activate to Row Activate Minimum (t
RRD
)
RAS to CAS Delay Min. (t
RCD
)
Minimum RAS Pulse Width
Module Bank Density
Unused Storage Locations
SPD Data Revision Code
Checksum for Byte 0 to 62
Manufacturer’s Information: Unused Storage
Vendor Specific Data: Unused Storage
Unused Storage Locations
128 Byte
256 Byte
SDRAM
11
9
2 bank
64 bit
+0
LVTTL
10/12/15 ns
8.5/8.5/9 ns
Non-Parity
Self, Normal
×
8
0
1 Cycle
1, 2, 4, 8, Page
2 bank
2, 3
0
0
UN-buffer
*1
15/17/20 ns
9/9/10 ns
No Support
No Support
30/35/40 ns
30/30/30 ns
30/30/30 ns
60/65/70 ns
32 MByte
—
0
*2
—
—
—
08h
04h
0Bh
09h
02h
40h
00h
01h
A0h
85h
00h
80h
08h
00h
01h
8Fh
02h
06h
01h
01h
00h
06h
F0h
90h
00h
00h
1Eh
1Eh
1Eh
3Ch
08h
00h
00h
B2h
00h
00h
—
08h
04h
0Bh
09h
02h
40h
00h
01h
C0h
85h
00h
80h
08h
00h
01h
8Fh
02h
06h
01h
01h
00h
06h
FFh
90h
00h
00h
23h
1Eh
1Eh
41h
08h
00h
00h
79h
00h
00h
—
08h
04h
0Bh
09h
02h
40h
00h
01h
F0h
90h
00h
80h
08h
00h
01h
8Fh
02h
06h
01h
01h
00h
06h
FFh
A0h
00h
00h
28h
1Eh
1Eh
46h
08h
00h
00h
24h
00h
00h
—
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TBD
TBD
Upper V
CC
tolerance
Lower V
CC
tolerance
Supported
Write 1
/Read Burst
Supported
Precharge
All
Supported
Auto-
Precharge
Supported
Early RAS
Precharge
0
0
0
0
0
1
1
0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB8508S064CE-100 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:8 M x 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM |
| MB85101BAN | 制造商:MURATA 制造商全称:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB85101BBN | 制造商:MURATA 制造商全称:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB85101CAN | 制造商:MURATA 制造商全称:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB85101CBN | 制造商:MURATA 制造商全称:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
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