参数资料
型号: MB8504S072AC-100
厂商: Fujitsu Limited
英文描述: CMOS 4M×72Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4M×72位 同步动态RAM)
中文描述: 4米× 72Bit的CMOS同步动态随机存取存储器(SDRAM)的CMOS(4分× 72位同步动态RAM)的
文件页数: 12/15页
文件大小: 362K
代理商: MB8504S072AC-100
12
MB8504S072AC-100/-84/-67
Notes:
*1. Assumes t
RCD
and t
CAC
are satisfied.
*2. t
AC
also specifies the access time at burst mode except for first access.
*3. Specified where output buffer is no longer driven.
*4. Actual clock count of t
RC
(I
RC
) will be sum of clock count of t
RAS
(I
RAS
) and t
RP
(I
RP
).
*5. t
RAC
is a reference value. Maximum value is obtained from the sum of t
RCD
(min) and t
CAC
(max).
*6. Assumes t
RAC
and t
AC
are satisfied.
*7. Operation within the t
RCD
(min) ensures that t
RAC
can be met; if t
RCD
is greater than the specified t
RCD
(min), access time is determined by t
CAC
and t
AC
.
*8. All base values are measured from the clock edge at the command input to the clock edge for the next
command input.
All clock counts are calculated by a simple formula:
clock count equals base value divided by clock period (round off to a whole number).
*9. The I
CAC
(CAS latency: CL) is programmed by the mode register.
*10. An initial pause (DESL on NOP) of 200
μ
s is required after power-up followed by a minimum of eight
Auto-refresh cycles.
*11. 1.4 V or V
REF
is the reference level for measuring timing of signals.
Transition times are measured between V
IH
(min) and V
IL
(max).
*12. AC characteristics assume t
T
= 1 ns and 30 pF of capacitive load.
*Source: See MB81117822A Data Sheet for details on the electricals.
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MB8504S072AC-67 CMOS 4M×72Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4M×72位 同步动态RAM)
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MB8504S072AD-67 CMOS 4M×72Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4M×72位 同步动态RAM)
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