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参数资料
| 型号： | MB8504S072AD-84 |
| 厂商： | Fujitsu Limited |
| 英文描述： | CMOS 4M×72Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4M×72位 同步动态RAM) |
| 中文描述： | 4米× 72Bit的CMOS同步动态随机存取存储器（SDRAM）的CMOS（4分× 72位同步动态RAM）的 |
| 文件页数： | 1/14页 |
| 文件大小： | 359K |
| 代理商： | MB8504S072AD-84 |
DS05-11114-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
Buffered
4 M
×
SYNCHRONOUS DYNAMIC RAM DIMM
MB8504S072AD-100/-84/-67
72 BIT
200-pin, 1-bank, based on 4 M
×
4 BIT SDRAMs with PLL
I
DESCRIPTION
The Fujitsu MB8504S072AD is a fully decoded, CMOS Synchronous Dynamic Random Access Memory
(SDRAM) module consisting of eighteen MB81117422A devices which organized as two banks of 1 M
This module is possible to minimize the skews of input signals such as clock and address signal by the PLL clock
driver and register buffers mounted. The MB8504S072AD is optimized for those applications requiring high speed,
high performance and large memory storage, and high density memory organizations.
This module is ideally suited for supercomputers, workstations, high-end PCs, laser printers, high resolution
graphic adapters, accelerators, and other applications where a simple interface is needed.
×
8 bits.
I
PRODUCT LINE & FEATURES
Parameter
MB8504S072AD-100
100 MHz max.
10 ns max. (CL = 4)
15 ns max. (CL = 3)
54.5 ns max.
24.5 ns max.
9 ns max. (CL = 4)
9.5 ns max. (CL = 3)
9968 mW max.
572 mW max.
MB8504S072AD-84
84 MHz max.
12 ns max. (CL = 4)
17 ns max. (CL = 3)
56.5 ns max.
26.5 ns max.
9 ns max. (CL = 4)
9.5 ns max. (CL = 3)
9122 mW max.
508 mW max.
MB8504S072AD-67
67 MHz max.
15 ns max. (CL = 4)
20 ns max. (CL = 3)
60.5 ns max.
30.5 ns max.
9.5 ns max. (CL = 4)
10.5 ns max. (CL = 3)
8276 mW max.
443 mW max.
Clock Frequency
Burst Mode Cycle Time
RAS Access Time
CAS Access Time
Output Valid from Clock
Power
Dissipation
Burst Mode
Power Down Mode
Buffered 200-pin DIMM Socket Type
(Lead pitch: 1.27 mm)
Conformed to JEDEC Standard
Organization: 4,194,304 words
×
72 bits (ECC)
Memory: MB81117422A (4 M
×
4, 2-bank)
×
18 pcs.
3.3 V
±
0.3 V Supply Voltage
All input/output LVTTL compatible
2048 Refresh Cycle every 32.8 ms (Burst Refresh)
Auto and Self Refresh
CKE Power Down Mode
Output Enable and Input Data Mask
PLL Clock Driver/Register Buffer/Input Buffer
Module size:
1.5” (height)
×
6.05” (length)
×
0.16” (thick)
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相关代理商/技术参数 |
参数描述 |
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| MB8508S064CE-100 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:8 M x 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM |
| MB85101BAN | 制造商:MURATA 制造商全称:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB85101BBN | 制造商:MURATA 制造商全称:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB85101CAN | 制造商:MURATA 制造商全称:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB85101CBN | 制造商:MURATA 制造商全称:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
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