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参数资料
| 型号： | MB8504S072AD-84 |
| 厂商： | Fujitsu Limited |
| 英文描述： | CMOS 4M×72Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4M×72位 同步动态RAM) |
| 中文描述： | 4米× 72Bit的CMOS同步动态随机存取存储器（SDRAM）的CMOS（4分× 72位同步动态RAM）的 |
| 文件页数： | 10/14页 |
| 文件大小： | 359K |
| 代理商： | MB8504S072AD-84 |
10
MB8504S072AD-100/-84/-67
(2) BASE VALUES FOR CLOCK COUNT/LATENCY
(3) CLOCK COUNT FORMULA (*8)
(4) LATENCY (The latency values on these parameters are fixed regardless of clock period.)
No.
Parameter
Notes
Symbol
MB8504S072AD
-100
MB8504S072AD
-84
MB8504S072AD
-67
Unit
Min.
Max.
Min.
Max.
Min..
Max.
1
RAS Cycle Time
*4
t
RC
90
—
100
—
110
—
ns
2
RAS Access Time
*5
t
RAC
—
54.5
—
56.5
—
60.5
ns
3
CAS Access Time
*6, *9
t
CAC
—
24.5
—
26.5
—
30.5
ns
4
RAS Precharge Time
t
RP
30
—
35
—
40
—
ns
5
RAS Active Time
t
RAS
60
100000
65
100000
70
100000
ns
6
RAS to CAS Delay Time
*7
t
RCD
30
—
30
—
30
—
ns
7
Write Recovery Time
t
WR
10
—
12
—
15
—
ns
8
Write Precharge Time
t
RWL
10
—
12
—
15
—
ns
9
RAS to RAS Bank Active
Delay Time
t
RRD
30
—
30
—
30
—
ns
No.
Parameter
SymbolMB85-100
MB8504S072AD
-84
MB8504S072AD
-67
Unit
1
CKE to Clock Disable
I
CKE
2
2
2
Cycle
2
DQM to Output in High-Z
I
DQZ
3
3
3
Cycle
3
DQM to Input Data Delay
I
DQD
1
1
1
Cycle
4
Last Output to Write Command
Delay
I
OWD
1
1
1
Cycle
5
Write Command to Input Data
Delay
I
DWD
1
1
1
Cycle
6
Precharge to
Output in High-Z Delay
CL = 4
I
ROH
4
4
4
Cycle
CL = 3
3
3
3
Cycle
7
Mode Register Access to Bank
Active (min)
I
MRD
2
2
2
Cycle
8
CAS to CAS Delay (min)
I
CCD
1
1
1
Cycle
9
CAS Bank Delay (min)
I
CBD
1
1
1
Cycle
Clock
≥
Base Value
Clock Period
(Round off a whole number)
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