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参数资料
| 型号： | MB8504S072AD-84 |
| 厂商： | Fujitsu Limited |
| 英文描述： | CMOS 4M×72Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4M×72位 同步动态RAM) |
| 中文描述： | 4米× 72Bit的CMOS同步动态随机存取存储器（SDRAM）的CMOS（4分× 72位同步动态RAM）的 |
| 文件页数： | 8/14页 |
| 文件大小： | 359K |
| 代理商： | MB8504S072AD-84 |
8
MB8504S072AD-100/-84/-67
I
DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)
Notes:
*1. Voltages referenced to V
SS
(= 0 V)
*2. I
CC
depends on the output termination, load conditions, clock cycle rate and signal clock rate.
The specified values are obtained with the output open and no termination register.
*3. An initial pause (DESL on NOP) of 200
μ
s is required after power-on followed by a minimum of eight
Auto-refresh cycles.
Parameter
Notes
Symbol
Condition
Value
Unit
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–10
–10
75
—
Max.
1701
1584
1467
2576
2358
2140
159
141
123
636
621
607
636
621
607
996
981
967
2769
2534
2299
2098
1899
1701
159
141
123
10
10
—
–75
Operating Current
(Average Power
Supply Current)
*2
MB8504S072AD-100
MB8504S072AD-84
MB8504S072AD-67
MB8504S072AD-100
MB8504S072AD-84
MB8504S072AD-67
MB8504S072AD-100
MB8504S072AD-84
MB8504S072AD-67
MB8504S072AD-100
MB8504S072AD-84
MB8504S072AD-67
MB8504S072AD-100
MB8504S072AD-84
MB8504S072AD-67
MB8504S072AD-100
MB8504S072AD-84
MB8504S072AD-67
MB8504S072AD-100
MB8504S072AD-84
MB8504S072AD-67
MB8504S072AD-100
MB8504S072AD-84
MB8504S072AD-67
MB8504S072AD-100
MB8504S072AD-84
MB8504S072AD-67
I
CC1S
No Burst;
t
CK
= min
t
RC
= min
One Bank Active
No Burst;
t
CK
= min
t
RC
= min
All Banks Active
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
I
CC1D
Precharge Standby
Current (Power
Supply Current)
*2
I
CC2P
CKE = V
IL
, t
CK
= min
All Banks Idle
I
CC2N
CKE = V
IH
, t
CK
= min
All Banks Idle
Active Standby
Current (Power
Supply Current)
*2
I
CC3P
CKE = V
IL
, t
CK
= min
Any Bank Active
I
CC3N
CKE = V
IH
, t
CK
= min
Any Bank Active
Burst Mode Current
(Average Power
Supply Current)
*2
I
CC4
t
CK
= min
Auto-refresh Current
(Average Power
Supply Current)
*2
I
CC5
Auto Refresh
t
CK
= min
t
RC
= min
t
RRD
= min
Self-refresh Current
(Average Power
Supply Current)
I
CC6
t
CK
= V
IL
Input Leakage Current (All inputs except DQ)
I
I (L)
V
IN
= 0 V
V
IN
= V
CC
V
IN
= 0.0 V
V
IN
= 2 V
Output is disabled (Hi-Z)
0 V
≤
V
OUT
≤
V
CC
3.0 V
≤
V
CC
≤
3.6 V
μ
A
Input Hold Current
(All inputs except CLK, PDE, DQ)
I
I (Hold)
μ
A
Output Leakage Current (All DQ)
I
O (L)
–10
10
μ
A
LVTTL Output
High Voltage
LVTTL Output
Low Voltage
*1
V
OH
I
OH
= –2.0 mA
2.4
—
V
*1
V
OL
I
OL
= +2.0 mA
—
0.4
V
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