参数资料
型号: MB88154APNF-G-113-JNERE1
厂商: FUJITSU LTD
元件分类: 时钟产生/分配
英文描述: 40 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 3.90 X 5.05 MM, 1.75 MM HEIGHT, 1.27 MM PITCH, PLASTIC, SOP-8
文件页数: 15/20页
文件大小: 541K
代理商: MB88154APNF-G-113-JNERE1
MB88154A
4
DS04-29129-2E
■ HANDLING DEVICES
Preventing Latch-up
A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an
input or output pin or (b) a voltage higher than the rating is applied between VDD pin and VSS pin. The latch-up,
if it occurs, significantly increases the power supply current and may cause thermal destruction of an element.
When you use this device, be very careful not to exceed the maximum rating.
Handling unused pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or
pull-down resistor.
Unused output pin should be opened.
The attention when the external clock is used
Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock.
Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin.
Power supply pins
Please design connecting the power supply pin of this device by as low impedance as possible from the current
supply source.
We recommend connecting electrolytic capacitor (about 10
μF) and the ceramic capacitor (about 0.01 μF) in
parallel between VSS pin and VDD pin near the device, as a bypass capacitor.
Oscillation circuit
Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that
electric wiring of XIN or XOUT pin and the resonator do not intersect other wiring.
Design the printed circuit board that surrounds the XIN and XOUT pins with ground.
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