参数资料
型号: MB91108PFV
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP120
封装: PLASTIC, LQFP-120
文件页数: 68/96页
文件大小: 1342K
代理商: MB91108PFV
MB91107/108
70
(5) Normal Bus Access Read/write Operation
(VCC
= 3.0 V to 3.6 V, AVSS = VSS = 0.0 V, TA = 0 °C to +70 °C)
*1: When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC
× extended cycle number for
delay) to this rating.
*2: Rating at a gear cycle of
× 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8, respectively.
Equation: (2 – n/2)
× tCYC – 25
Parameter
Sym-
bol
Pin name
Condi-
tion
Value
Unit
Remarks
Min.
Max.
CS0 to CS7 delay time
tCHCSL
CLK
CS0 to CS7
15
ns
CS0 to CS7 delay time
tCHCSH
15
ns
Address delay time
tCHAV
CLK
A24 to A00
15
ns
Data delay time
tCHDV
CLK
D31 to D16
15
ns
RD delay time
tCLRL
CLK
RD
15
ns
RD delay time
tCLRH
15
ns
WR0, WR1 delay time
tCLWL
CLK
WR0 to WR1
15
ns
WR0, WR1 delay time
tCLWH
15
ns
Valid address
→ valid data
input time
tAVDV
A24 to A00
D31 to D16
3
/ 2 × tCYC 25 ns
*1
*2
RD
↓→ valid data input time
tRLDV
RD
D31 to D16
tCYC
10
ns
*1
Data set up
→ RD ↑ time
tDSRH
10
ns
RD
↑→ data hold time
tRHDX
0
ns
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