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参数资料
| 型号： | MB91F233LPMC1-GE1 |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 33.6 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封装： | PLASTIC, LQFP-120 |
| 文件页数： | 15/68页 |
| 文件大小： | 1635K |
| 代理商： | MB91F233LPMC1-GE1 |
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MB91230 Series
22
DS07–16506–3E
Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS
register to be updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
it performs operations before and after the EIT as specified in either case.
The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) acceptance of a user interrupt, (b) single-stepped, or (c) breaks in response to a data
event or emulator menu :
1) The D0 and D1 flags are updated in advance.
2) An EIT handling routine (user interrupt or emulator) is executed.
3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed, and the D0 and D1 flags are
updated to the same values as in 1).
The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed
to allow the interrupt.
1) The PS register is updated in advance.
2) An EIT handling routine (user interrupt) is executed.
3) Upon returning from the EIT, the above instructions are executed, and the PS register is updated to the
same value as in 1).
Watchdog Timer
The watchdog timer built in this model monitors a program that it defers a reset within a certain period of
time. The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer
function from being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog
timer keeps on operating programs until it resets the CPU.
As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops
program execution.
For those conditions to which this exception applies, see Section “
Watchdog timer suspension (Automatic
generation postponement) ” in “
■Time-base Counter” of Section “3.11.7 Peripheral Circuits in the Clock
Control Unit” in Hardware manual.
Step execution of RETI instruction
If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is exe-
cuted repeatedly after step execution. This will prevent the main routine and low-interrupt-level programs
from being executed.
Do not execute step of RETI instruction for escape.
Disable the corresponding interrupt and execute debugger when the corresponding interrupt routine no
longer needs debugging.
Operand Break
Do not apply a data event break to access to the area containing the address of a system stack pointer.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB91F233PFF-GE1 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F248 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F248PFV-GSE1 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F248S | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F248SPFV-GSE1 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
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