参数资料
型号: MB91F318RPMC-GXXX-XXXXE1
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 40.8 MHz, RISC MICROCONTROLLER, PQFP176
封装: 24 X 24 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-176
文件页数: 59/71页
文件大小: 575K
代理商: MB91F318RPMC-GXXX-XXXXE1
MB91319R Series
62
(11) I2C timing
At master mode operating
(Ta
= 10 °C to + 70 °C, VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V)
*1 : M
= Resource clock cycle (ns)
*2 : A Fast-mode I2C bus device can be used for a standard mode I2C bus system as long as the device satisfies
a requirement of “tSUDAT
≥ 250 ns”.
When the device does not extend the “L” period of the SCL signal, the next data must be outputted to the SDA
line within 1250 ns (maximum SDA/SCL rise time
+ tSUDAT) in which the SCL line is released.
*3 : For use at over 100 kHz, set the resource clock to at least 6 MHz.
*4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines.
Parameter
Sym-
bol
Conditions
Typical mode
High-speed mode*3
Unit
Remarks
Min
Max
Min
Max
SCL clock frequency
fSCL
R
= 1 k
C
= 50 pF*4
0
100
0
400
kHz
“L” period of SCL clock
tLOW
4.7
1.3
s
“H” period of SCL clock
tHIGH
4.0
0.6
s
Bus free time between
[STOP condition] and
[START condition]
tBUS
4.7
1.3
s
SCL
↓ → SDA output
delay time
tDLDAT
5
× M*1
5
× M*1
ns
Setup time of [repeat
START condition]
SCL
↑ → SDA↓
tSUSTA
4.7
0.6
s
Hold time of [repeat
START condition]
SDA
↓ → SCL↓
tHDSTA
4.0
0.6
s
After that, the
first clock pulse
is generated.
Setup time of [STOP
condition]
SCL
↑ → SDA↑
tSUSTO
4.0
0.6
s
SDA data input hold
time (vs. SCL
↓)
tHDDAT
2
× M*1
2
× M*1
s
SDA data input setup
time (vs. SCL
↑)
tSUDAT
250
100*2
ns
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