参数资料
型号: MB91F366GB
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 63.33 MHz, RISC MICROCONTROLLER, PQFP120
封装: PLASTIC, QFP-120
文件页数: 15/64页
文件大小: 800K
代理商: MB91F366GB
FME / EMDC / Br - mb91f365g_f366g_ds.fm
22
9-Jan-02
Bit 0: LPM:
0: normal mode
1: low power mode, can be used when CPU frequency is below 5 MHz
Note: This register provides no functionality on MB91366GA, however, when writing to this register always
write “11” to bits 6 and 5.
2.1.3 Flash/ROM Wait Control Register (FMWT)
Bit 6: This bit is reserved, always set this bits to "0" when writing to this register.
Bits 5,4: These bits control the length of the high pulse for the ATDIN signal for the flash memory on F365F/
F366GB, these bits have no function on 366GA.
Bit 3: EQINH: This bit controls the falling edge of the EQIN signal or the flash memory on F365F/F366GB, this bit
has no function on 366GA.
0: falling edge of EQIN at falling edge of FWAITR;
1: falling edge of EQIN half cycle after falling edge of FWAITR;
Bit 2,1,0: WTC2,1,0: Wait Cycle bits
WTC2-0 are used to insert auto wait cycles for flash memory and ROM memory access.
address
bit 7
bit6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0000700
4H
----
FAC1
FAC0
EQINH
WTC2
WTC1
WTC0
access
R/W
initial
value
0000
011
value
after
Boot
ROM
0010
011
FAC1
FAC0
length of high pulse for ATDIN
0
0.5 cycles of CLKB
0
1
1 cycle of CLKB
1
0
1.5 cycles of CLKB
1
2 cycles of CLKB
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