参数资料
型号: MB91F475PMC1-GE1
厂商: Fujitsu Semiconductor America Inc
文件页数: 42/94页
文件大小: 0K
描述: IC MCU 256KB FLASH 144-LQFP
标准包装: 1
系列: FR MB91470
核心处理器: FR60 RISC
芯体尺寸: 32-位
速度: 80MHz
连通性: EBI/EMI,I²C,FIFO,SIO
外围设备: DMA,PWM,WDT
输入/输出数: 113
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 5.5 V
数据转换器: A/D 12x8/10b,4x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 144-LQFP
包装: 托盘
其它名称: 865-1093
49
32015G–AVR32–09/09
AT32AP7001
8.8
PICO Instructions
8.8.1
PICO Instructions Nomenclature
8.8.1.1
Registers and Operands
R{d, s, …}
The uppercase ‘R’ denotes a 32-bit (word) register.
Rd
The lowercase ‘d’ denotes the destination register number.
Rs
The lowercase ‘s’ denotes the source register number.
Rb
The lowercase ‘b’ denotes the base register number for indexed addressing modes.
Ri
The lowercase ‘i’ denotes the index register number for indexed addressing modes.
Rp
The lowercase ‘p’ denotes the pointer register number.
IN{x, y, z}
The uppercase ‘IN’ denotes a pixel in the INPIXn registers.
INx
The lowercase ‘x’ denotes the first input pixel number for the PICO operation instructions.
INy
The lowercase ‘y’ denotes the second input pixel number for the PICO operation instructions.
INz
The lowercase ‘z’ denotes the third input pixel number for the PICO operation instructions.
OUTd
The uppercase ‘OUT’ denotes a pixel in the OUTPIXn registers.
OUTd
The lowercase ‘d’ denotes the destination pixel number for the PICO operation instructions.
Pr
PICO register. See Section 8.7.1 ”Register File” on page 31 for a complete list of registers.
PrHi:PrLo
PICO register pair. Only register pairs corresponding to valid coprocessor double registers are valid.
E.g. INPIX1:INPIX2 (cr1:cr0). The low part must correspond to an even coprocessor register number
n and the high part must then correspond to coprocessor register n+1. See Table 8-1 on page 31
for a mapping between PICO register names and coprocessor register numbers.
PC
Program Counter, equal to R15
LR
Link Register, equal to R14
SP
Stack Pointer, equal to R13
PICORegList
Register List used in the picoldm and picostm instructions. See instruction description for which
register combinations are allowed in the register list.
disp
Displacement
sa
Shift amount
[i]
Denotes bit i in a immediate value. Example: imm6[4] denotes bit 4 in an 6-bit immediate value.
[i:j]
Denotes bit i to j in an immediate value.
Some instructions access or use doubleword operands. These operands must be placed in two consecutive register
addresses where the first register must be an even register. The even register contains the least significant part and
the odd register contains the most significant part. This ordering is reversed in comparison with how data is
organized in memory (where the most significant part would receive the lowest address) and is intentional.
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