参数资料
型号: MB91F475PMC1-GE1
厂商: Fujitsu Semiconductor America Inc
文件页数: 93/94页
文件大小: 0K
描述: IC MCU 256KB FLASH 144-LQFP
标准包装: 1
系列: FR MB91470
核心处理器: FR60 RISC
芯体尺寸: 32-位
速度: 80MHz
连通性: EBI/EMI,I²C,FIFO,SIO
外围设备: DMA,PWM,WDT
输入/输出数: 113
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 5.5 V
数据转换器: A/D 12x8/10b,4x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 144-LQFP
包装: 托盘
其它名称: 865-1093
95
32015G–AVR32–09/09
AT32AP7001
Figure 11-2. PLL with control logic and filters
11.5.3.1
Enabling the PLL
PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1
as clock source. The PLLDIV and PLLMUL bitfields must be written with the division and multipli-
cation factor, respectively, creating the PLL frequency:
f
PLL = (PLLMUL+1) / (PLLDIV+1) fOSC
The LOCKn flag in ISR is set when PLLn becomes locked. The bit will stay high until cleared by
writing 1 to ICR:LOCKn. The Power Manager interrupt can be triggered by writing IER:LOCKn to
1.
Note that the input frequency for the PLL must be within the range inidicated in the Electrical
Characteristics chapter. The input frequency for the PLL relates to the oscillator frequency and
PLLDIV setting as follows:
f
PLLIN = 2 fOSC / (PLLDIV+1)
PLL
Output
Divider
Input
Divider
LFT
0
1
Osc0 clock
Osc1 clock
PLLOSC
PLLEN
PLLOPT
PLLMUL
PLLDIV
Lock
Suppression
PLLCOUNT
LOCK
Mask
PLL clock
C1
R1
C2
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