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参数资料
| 型号： | MB91F482PMC-GE1 |
| 厂商： | Fujitsu Semiconductor America Inc |
| 文件页数： | 89/94页 |
| 文件大小： | 0K |
| 描述： | IC MCU 256KB FLASH 100-LQFP |
| 标准包装： | 1 |
| 系列： | FR MB91480 |
| 核心处理器： | FR60 RISC |
| 芯体尺寸： | 32-位 |
| 速度： | 80MHz |
| 连通性： | I²C，FIFO，SIO |
| 外围设备： | DMA，PWM，WDT |
| 输入/输出数： | 77 |
| 程序存储器容量： | 256KB（256K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 16K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 数据转换器： | A/D 14x8/10b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 包装： | 托盘 |
| 其它名称： | 865-1097 |
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91
32015G–AVR32–09/09
AT32AP7001
11. Power Manager (PM)
Rev: 1.0.2.8
11.1
Features
Controls oscillators and PLLs
Generates clocks and resets for digital logic
Supports 2 high-speed crystal oscillators
Supports 2 PLLs
Supports 32KHz ultra-low power oscillator
On-the fly frequency change of CPU, HSB, and PB frequency
Sleep modes allow simple disabling of logic clocks, PLL’s and oscillators
Module-level clock gating through maskable peripheral clocks
Wake-up from interrupts or external pin
Generic clocks with wide frequency range provided
Automatic identification of reset sources
11.2
Description
The Power Manager (PM) controls the oscillators, PLL’s, and generates the clocks and resets in
the device. The PM controls two fast crystal oscillators, as well as two PLL’s, which can multiply
the clock from either oscillator to provide higher frequencies. Additionally, a low-power 32KHz
oscillator is used to generate a slow clock for real-time counters.
The provided clocks are divided into synchronous and generic clocks. The synchronous clocks
are used to clock the main digital logic in the device, namely the CPU, and the modules and
peripherals connected to the HSB, PBA, and PBB buses. The generic clocks are asynchronous
clocks, which can be tuned precisely within a wide frequency range, which makes them suitable
for peripherals that require specific frequencies, such as timers and communication modules.
The PM also contains advanced power-saving features, allowing the user to optimize the power
consumption for an application. The synchronous clocks are divided into four clock domains, for
the CPU, and modules on the HSB, PBA, and PBB buses. The four clocks can run at different
speeds, so the user can save power by running peripherals at a relatively low clock, while main-
taining a high CPU performance. Additionally, the clocks can be independently changed on-the
fly, without halting any peripherals. This enables the user to adjust the speed of the CPU and
memories to the dynamic load of the application, without disturbing or re-configuring active
peripherals.
Each module also has a separate clock, enabling the user to switch off the clock for inactive
modules, to save further power. Additionally, clocks and oscillators can be automatically
swithced off during idle periods by using the sleep instruction on the CPU. The system will return
to normal on occurence of interrupts or an event on the WAKE_N pin.
The Power Manager also cointains a Reset Controller, which collects all possible reset sources,
generates hard and soft resets, and allows the reset source to be identifed by software.
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