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参数资料
| 型号： | MB95F136JBWPF-GE1 |
| 厂商： | Fujitsu Semiconductor America Inc |
| 文件页数： | 14/64页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32KB FLASH 28SOP |
| 标准包装： | 1 |
| 系列： | F²MC MB95130MB |
| 核心处理器： | F²MC-8FX |
| 芯体尺寸： | 8-位 |
| 速度： | 16MHz |
| 连通性： | LIN，SIO，UART/USART |
| 外围设备： | LVD，POR，PWM，WDT |
| 输入/输出数： | 19 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.4 V ~ 5.5 V |
| 数据转换器： | A/D 8x8/10b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 28-SOP |
| 包装： | 管件 |
| 其它名称： | 865-1075 |
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MB95130MB Series
21
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
The DP specifies the area for mapping instructions (16 different types of instructions such as MOV A and dir)
using direct addresses to 0080H to 00FFH.
The CCR consists of the bits indicating arithmetic operation results or transfer data content and the bits that
control CPU operations at interrupt.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
XXXB (no effect to mapping)
0000H to 007FH
0000H to 007FH (without mapping)
000B (initial value)
0080H to 00FFH
0080H to 00FFH (without mapping)
001B
0100H to 017FH
010B
0180H to 01FFH
011B
0200H to 027FH
100B
0280H to 02FFH
101B
0300H to 037FH
110B
0380H to 03FFH
111B
0400H to 047FH
H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is cleared to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL1
IL0
Interrupt level
Priority
00
0
High
Low (no interruption)
01
1
10
2
11
3
N flag
: Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
Z flag
:
Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
V flag
: Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
C flag
: Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
Rule for Conversion of Actual Addresses in the General-purpose Register Area
Generated address
RP upper
OP code lower
“0”
“1”
R4
R3
R2
R1
R0
b2
b1
b0
A7
A6
A5
A4
A3
A2
A1
A0
A15 A14 A13 A12 A11 A10
A9
A8
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB95F136JBWPFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:8-bit Microcontrollers |
| MB95F136JS | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
| MB95F136JSPFV-GE1 | 制造商:FUJITSU 功能描述:8BIT MCU 32K FLASH 1K RAM SOP28 |
| MB95F136JW | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
| MB95F136KSPF-GE1 | 制造商:FUJITSU 功能描述: |
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