参数资料
型号: MB95F168JAPMC1-GE1
厂商: Fujitsu Semiconductor America Inc
文件页数: 32/76页
文件大小: 0K
描述: IC MCU FLASH 60K ROM 64LQFP
标准包装: 1
系列: F²MC MB95160MA
核心处理器: F²MC-8FX
芯体尺寸: 8-位
速度: 16MHz
连通性: I²C,LIN,SIO,UART/USART
外围设备: LCD,LVD,POR,PWM,WDT
输入/输出数: 52
程序存储器容量: 60KB(60K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 5.5 V
数据转换器: A/D 8x8/10b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 64-LQFP
包装: 托盘
产品目录页面: 722 (CN2011-ZH PDF)
其它名称: 865-1078
MB95160MA Series
38
DS07–12624–3E
(2) Source Clock/Machine Clock
(Vcc
= 5.0 V ± 10%, Vss = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
Main clock divided by 2
PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
Sub clock divided by 2
PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
Source clock (no division)
Source clock divided by 4
Source clock divided by 8
Source clock divided by 16
Parameter
Sym-
bol
Condi-
tions
Value
Unit
Remarks
Min
Typ
Max
Source clock
cycle time*1
(Clock before setting
division)
tSCLK
61.5
2000
ns
When using main clock
Min : FCH
= 8.125 MHz,
PLL multiplied by 2
Max : FCH
= 1 MHz, divided by 2
7.6
61.0
μs
When using sub clock
Min : FCL
= 32 kHz, PLL multiplied by 4
Max : FCL
= 32 kHz, divided by 2
Source clock
frequency
FSP
0.50
16.25
MHz When using main clock
FSPL
16.384
131.072
kHz When using sub clock
Machine clock cycle
time*2
(Minimum instruction
execution time)
tMCLK
61.5
32000
ns
When using main clock
Min : FSP
= 16.25 MHz, no division
Max : FSP
= 0.5 MHz, divided by 16
7.6
976.5
μs
When using sub clock
Min : FSPL
= 131 kHz, no division
Max : FSPL
= 16 kHz, divided by 16
Machine clock
frequency
FMP
0.031
16.250
MHz When using main clock
FMPL
1.024
131.072
kHz When using sub clock
FCH
(main oscillation)
FCL
(sub oscillation)
Divided by 2
Main PLL
× 1
× 2
× 2.5
Divided by 2
Sub PLL
× 2
× 3
× 4
SCLK
( source clock )
MCLK
( machine clock )
Clock mode select bit
( SYCC : SCS1, SCS0 )
Division
circuit
× 1
× 1/4
× 1/8
× 1/16
× 4
Outline of clock generation block
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