参数资料
型号: MB95F572KPF-G-JNE2
厂商: FUJITSU LTD
元件分类: 微控制器/微处理器
英文描述: MICROCONTROLLER, PDSO8
封装: 5.30 X 5.24 MM, 2.10 MM HEIGHT, 1.27 MM PITCH, PLASTIC, M08, SOP-8
文件页数: 52/84页
文件大小: 3929K
代理商: MB95F572KPF-G-JNE2
MB95560H/570H/580H Series
56
DS702-00010-1v0-E
(6) LIN-UART Timing (available only on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/
F583H/F583K/F584H/F584K)
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 0)
(VCC = 5.0 V
± 10%, AVSS = VSS = 0.0 V, TA = 40°C to + 85°C)
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
Parameter
Symbol Pin name
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK
Internal clock
operation output pin:
CL = 80 pF
+ 1 TTL
5 tMCLK*3
—ns
SCK
↓→ SOT delay time
tSLOVI
SCK, SOT
50
+ 50
ns
Valid SIN
→ SCK ↑
tIVSHI
SCK, SIN
tMCLK*3
+ 80
ns
SCK
↑→ valid SIN hold time
tSHIXI
SCK, SIN
0
ns
Serial clock “L” pulse width
tSLSH
SCK
External clock
operation output pin:
CL = 80 pF
+ 1 TTL
3 tMCLK*3
tR
—ns
Serial clock “H” pulse width
tSHSL
SCK
tMCLK*3
+ 10
ns
SCK
↓→ SOT delay time
tSLOVE
SCK, SOT
2 tMCLK*3
+ 60 ns
Valid SIN
→ SCK ↑
tIVSHE
SCK, SIN
30
ns
SCK
↑→ valid SIN hold time
tSHIXE
SCK, SIN
tMCLK*3
+ 30
ns
SCK fall time
tF
SCK
10
ns
SCK rise time
tR
SCK
10
ns
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